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pi7c9x7958 pci express ? octal uart datasheet revision 1.4 march 2011 3545 north 1st street, san jose, ca 95134 telephone: 1-877-pericom, (1-877-737-4266) fax: 408-435-1100 internet: http://www.pericom.com 11-0039
pi7c9x7958 pci express? octal uart datasheet page 2 of 71 march 2011 ? revision 1.4 pericom semiconductor disclaimer the information contained in this document is proprietary and confidential to pericom semiconductor cooperation (psc). no part of this document may be copied or reproduced in any form or by any means without prior written consent of psc. the information in this document is subjected to change without notice. psc retains the right to make changes to this document at any time without notice. while the information contained in this document has been checked for accuracy, such information is preliminary, and psc does not warrant the accuracy and completeness of such information. psc does not assume any liability or responsibility for damages arising from any use of the information contained in this document. life support policy pericom semiconductor corporation?s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of psc. 1) life support devices or system are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2) a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pericom semiconductor corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a pericom semiconductor product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of pericom semiconductor corporation. all other trademarks are of their respective companies. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 3 of 71 march 2011 ? revision 1.4 pericom semiconductor revision history date revision number description 9/05/07 0.1 preliminary datasheet 10/31/07 0.2 fixed the diagrams corrected chapter 4.2 pin description (rref, gpio[7] eeprom organization pin, rts[0] eeprom bypass pin) updated chapter 6 pci express registers(6.2.42 [3], 6.2.36 uart driver setting, 6.2.41 gpio control register ) revised chapter 7.1 registers in i/o mode updated chapter 11 ordering info updated chapter 8 eeprom 4/22/08 0.3 updated 1 features (clock prescaler, data frame size, power dissipation) corrected 3 general description updated 4 pin assignment (description for shared pins added, mode_sel changed to driver_sel, vaux changed to vddcaux, wakeup_l, clkinp, clkinn) added 5.2.4 mode selection, 5.2.5 450/550 mode, 5.2.6 enhanced 550 mode, 5.2.7 enhanced 950 mode corrected 5.2.8 transmit and receive fifos, 5.2.9 automated flow control modified 5.2.12 baud rate generation updated 6 pci express register description (6.2.36, 6.2.42) updated format (6.2.20, 6.2.36, 6.2.54, 6.2.55, 6.2.57) updated chapter 7 uart register description (7.1.6 lcr bit[5:0], 7.1.7 mcr bit[5] and bit[7], 7.1.9 msr bit[3:0], 7. 2.6 lcr bit[5:0], 7.2.7 mcr bit[5] and bit[7], 7.2.9 msr bit[3:0], 7.2.11 dll, 7.2.12 dlh, 7.2.13 efr, 7.2.18 acr bit[7:2], 7.2.23 cprm) updated chapter 8.3 eeprom space address map and description (00h, 0ah, 40h) added chapter 9 electrical specification corrected 9.2 dc specification updated 9.3 ac specification added 10 clock scheme 8/13/08 0.4 updated chapter 1 features (added industrial temperature range) updated 9.1 absolute maximum ratings: ambient temperature with power applied 11/25/08 1.0 updated 7.1.13 sample clock register and 7.2.27 sample clock register updated chapter 12 ordering information removed ?preliminary? and ?confidential? references 3/6/09 1.1 corrected figure 3-1 pi7c9x7958 block diagram (syn_uart_clk removed) corrected section 4.2.1 uart interface (synclk_in_en and syn_uart_clk removed) corrected figure 5-2 internal loopback in pi7c7958 corrected figure 5-3 crystal oscillator as the clock source (14.7456 mhz) corrected section 7.1.7 modem control register (bit[5]), 7.1.10 special function register (bit[4]), 7.2.7 modem control register (bit[5]), 7.2.10 special function register (b it[4]), 7.2.29 receive fifo data registers, 7.2.30 transmit fifo data register, 7.2.31 4/20/09 1.2 added internal pull-up and pull-down information to uart interface, system interface, test signal, and eeprom pins in section 4. 9/24/09 1.3 updated figure 5-3 crystal oscillator as the clock source updated section 6.2.24 message signaled interrupt (msi) next item pointer 8ch added section 6.2.25 message address register ? offset 90h added section 6.2.26 message upper address register ? offset 94h added section 6.2.27 message data register ? offset 98h 3/18/11 1.4 updated section 11 package information 11-0039
pi7c9x7958 pci express? octal uart datasheet page 4 of 71 march 2011 ? revision 1.4 pericom semiconductor table of contents 1. features ....................................................................................................................... .....................9 2. applications ................................................................................................................... ................9 3. general description ............................................................................................................ ...10 4. pin assignment................................................................................................................. ............11 4.1. pin list of 160-pin lfbga ......................................................................................................11 4.2. pin description .................................................................................................................... ..12 4.2.1. uart interface................................................................................................................1 2 4.2.2. pci express interface ..................................................................................................13 4.2.3. system interface............................................................................................................14 4.2.4. test signals................................................................................................................... ...14 4.2.5. eeprom interface..........................................................................................................15 4.2.6. power pins ..................................................................................................................... ...15 5. functional description ........................... .............................................................................1 6 5.1. configuration space ..........................................................................................................16 5.1.1. pci express configuration space .........................................................................................16 5.1.2. uart configuration space ...................................................................................................16 5.2. device operation..................................................................................................................17 5.2.1. configuration access .......................... .......................... .......................... ............. ................ ..17 5.2.2. i/o reads/writes............................................................................................................... .....17 5.2.3. memory reads/writes...... ......................... .......................... .......................... ......................... 17 5.2.4. mode selection ................................................................................................................. .....18 5.2.5. 450/550 mode ................................................................................................................... .....18 5.2.6. enhanced 550 mode .............................................................................................................. 18 5.2.7. enhanced 950 mode .............................................................................................................. 18 5.2.8. transmit and receive fifos .................... .......................... ........................ ..................... ......18 5.2.9. automated flow control........................................................................................................2 0 5.2.10. internal loopback.............................................................................................................. ....21 5.2.11. crystal oscillator ............................................................................................................. .....22 5.2.12. baud rate generation ........................................................................................................... 23 5.2.13. power management ............................................................................................................... 23 6. pci express register description .......................... .......................... ............. ..................24 6.1. register types .......................................................................................................................24 6.2. configuration registers.................................................................................................24 6.2.1. vendor id register ? offset 00h ..............................................................................25 6.2.2. device id register ? offset 00h................................................................................25 6.2.3. command register ? offset 04h.. .......................... ........................ ............... ............25 6.2.4. status register ? offset 04h......................................................................................26 6.2.5. revision id register ? offset 08h ............................................................................26 6.2.6. class code register ? offset 08 h............................................................................26 6.2.7. cache line register ? offset 0c h............................................................................27 6.2.8. master latency timer register ? o ffset 0ch ...................... ............. ..................27 6.2.9. header type register ? offset 0c h...................... .......................... .........................27 6.2.10. base address register 0 ? offset 10h.................. .......................... .........................27 6.2.11. base address register 1 ? offset 14h.................. .......................... .........................27 6.2.12. subsystem vendor register ? offset 2ch ............................................................27 6.2.13. subsystem id register ? offset 2c h............... .......................... ............. ..................27 11-0039
pi7c9x7958 pci express? octal uart datasheet page 5 of 71 march 2011 ? revision 1.4 pericom semiconductor 6.2.14. capabilities pointer register ? offset 34h.......................... ............. ..................28 6.2.15. interrupt line register ? offset 3ch....................................................................28 6.2.16. interrupt pin register ? offset 3ch......................................................................28 6.2.17. power management capability id register ? offset 80h...............................28 6.2.18. next item pointer register ? offset 80h.................. ......................... ...................28 6.2.19. power management capabilities re gister ? offset 80h . ............. ..................28 6.2.20. power management data register ? offset 84h ...............................................29 6.2.21. ppb support extensions ? offset 84h.................. .......................... .........................29 6.2.22. pm data register ? offset 84h...................................................................................29 6.2.23. message signaled interrupts (msi) ca pability id register 8ch ......... ..................29 6.2.24. message signaled interrupts (msi) next item pointer 8ch ..........................30 6.2.25. message address register ? offse t 90h.................... ......................... ...................30 6.2.26. message upper address register ? offset 94h ................... ............. ..................30 6.2.27. message data register ? offset 98h .......................................................................30 6.2.28. vpd capability id register ? off set 9ch ...............................................................30 6.2.29. next item pointer register ? o ffset 9ch ....................... ................... ...................30 6.2.30. vpd register ? offset 9ch .............. ......................... ........................ ............... ............30 6.2.31. vpd data register ? offset a0h .... ......................... ........................ ............... ............31 6.2.32. vendor specific capability id register ? offset a4h .................. ...................31 6.2.33. next item pointer register ? o ffset a4h .............................. ................... ............31 6.2.34. length register ? offset a4h ...................................................................................31 6.2.35. xpip csr0 ? offset a8h (test purpose only) ............... ........................ ............... ............31 6.2.36. xpip csr1 ? offset ach (test purpose only) ........ .......................... ................... ............31 6.2.37. replay time-out counter ? offset b0h .................................................................31 6.2.38. acknowledge latency timer ? offset b0h ..........................................................32 6.2.39. uart driver setting ? offset b4h ......................... ........................ ............... ............32 6.2.40. power management control parameter ? offset b8h ......................................................33 6.2.41. debug register 1 ? offset bch (test purpose only) ................................................33 6.2.42. debug register 2 ? offset c0h (test purpose only).................................................33 6.2.43. debug register 3 ? offset c4h (test purpose only).................................................33 6.2.44. debug register 4 ? offset c8h (test purpose only).................................................34 6.2.45. gpio control register ? offset d8h......................................................................34 6.2.46. eeprom control register ? offset dch...............................................................34 6.2.47. pci express capability id registe r ? offset e0h................. ............. ..................35 6.2.48. next item pointer register ? o ffset e0h .............................. ................... ............35 6.2.49. pci express capabilities register ? offset e0h .................................................35 6.2.50. device capabilities register ? of fset e4h............................ ............. ..................35 6.2.51. device control register ? offset e8h .................................................................36 6.2.52. device status register ? offset e8h .......................... ......................... ...................36 6.2.53. link capabilities register ? o ffset ech ......................... ................... ...................37 6.2.54. link control register ? offset f0h.......................................................................37 6.2.55. link status register ? offset f0h ...........................................................................38 6.2.56. pci express advanced error reporting capability id register ? offset 100h 38 6.2.57. capability version ? offset 100h ..................... .......................... ............. ..................38 6.2.58. next item pointer register ? offset 100h................ ......................... ...................39 6.2.59. uncorrectable error status regist er ? offset 104h .................. ...................39 6.2.60. uncorrectable error mask register ? offset 108h......... ............. ..................39 6.2.61. uncorrectable error severity register ? offset 10ch . ............. ..................40 6.2.62. correctable error status register ? offset 110h...........................................41 6.2.63. correctable error mask register ? offset 114h .............. ............. ..................41 6.2.64. advance error capabilities and control register ? offset 118h.............42 6.2.65. header log register ? offset from 11ch to 128h .................................................42 11-0039
pi7c9x7958 pci express? octal uart datasheet page 6 of 71 march 2011 ? revision 1.4 pericom semiconductor 7. uart register descript ion...................... ......................... ........................ ............... ............44 7.1. registers in i/o mode ..........................................................................................................44 7.1.1. receive holding register ? offset 00h ................................................................45 7.1.2. transmit holding register ? offset 00h..............................................................45 7.1.3. interrupt enable register ? offset 01h ..............................................................45 7.1.4. interrupt status register ? offse t 02h.................... ......................... ...................46 7.1.5. fifo control register ? offset 02h .......................................................................46 7.1.6. line control register ? offset 03h .................... .......................... .........................46 7.1.7. modem control register ? offset 04h ..................... ......................... ...................47 7.1.8. line status register ? offset 05 h ................... .......................... ............. ..................48 7.1.9. modem status register ? offset 06 h.......................... ......................... ...................49 7.1.10. special function register ? offse t 07h............ .......................... .........................49 7.1.11. divisor latch low register ? offset 00 h, lcr[7] = 1 ........................................50 7.1.12. divisor latch high register ? offset 01h, lcr[7] = 1.......................................50 7.1.13. sample clock register ? offset 02h, lcr[7] = 1 .................................................50 7.2. r egisters in m emory -m apping m ode .......................................................................................51 7.2.1. receive holding register ? offset 00h ................................................................52 7.2.2. transmit holding register ? offset 00h..............................................................53 7.2.3. interrupt enable register ? offset 01h ..............................................................53 7.2.4. interrupt status register ? offse t 02h.................... ......................... ...................53 7.2.5. fifo control register ? offset 02h .......................................................................54 7.2.6. line control register ? offset 03h .................... .......................... .........................54 7.2.7. modem control register ? offset 04h ..................... ......................... ...................55 7.2.8. line status register ? offset 05 h ................... .......................... ............. ..................56 7.2.9. modem status register ? offset 06 h.......................... ......................... ...................57 7.2.10. special function register ? offse t 07h............ .......................... .........................57 7.2.11. divisor latch low register ? offs et 08h .............................................................58 7.2.12. divisor latch high register ? offset 09h............................................................58 7.2.13. enhanced function register ? offset 0ah................... .................... ..................58 7.2.14. xon special character 1 ? offset 0b h....................... ......................... ...................59 7.2.15. xon special character 2 ? offset 0ch . ..................... .......................... ..................59 7.2.16. xoff special character 1 ? offset 0dh ................................................................59 7.2.17. xoff special character 2 ? offset 0eh ................................................................59 7.2.18. advance control register ? offset 0fh ..............................................................60 7.2.19. transmit interrupt trigger level ? offset 10h................. ............. ..................60 7.2.20. receive interrupt trigger level ? offset 11h ................... ............. ..................60 7.2.21. flow control low trigger level ? offset 12h .................. ............. ..................60 7.2.22. flow control high trigger level ? offset 13h ...............................................61 7.2.23. clock prescale register ? offset 14h..................................................................61 7.2.24. receive fifo data counter ? offset 15h, sfr[6] = 0..........................................61 7.2.25. line status register counter ? offset 15h, sfr[6] = 1 .................. ..................61 7.2.26. transmit fifo data counter ? off set 16h, sfr[7] = 1 .................... ...................61 7.2.27. sample clock register ? offset 16h, sfr[7] = 0 .................................................62 7.2.28. global line status register ? of fset 17h ......... ........................ ............... ............62 7.2.29. receive fifo data registers ? offset 100h ~ 17fh............... ............. ..................62 7.2.30. transmit fifo data registers ? offset 100h ~ 17fh ...........................................63 7.2.31. line status fifo registers ?offse t 180h ~ 1ffh ................... ............. ..................63 8. eeprom interface ............................................................................................................... ......64 8.1. auto mode eerpom access ...............................................................................................64 8.2. eeprom mode at reset ........................................................................................................64 8.3. eeprom space address map and description ..........................................................64 11-0039
pi7c9x7958 pci express? octal uart datasheet page 7 of 71 march 2011 ? revision 1.4 pericom semiconductor 9. electrical specification.....................................................................................................66 9.1. absolute maximum ratings ...........................................................................................66 9.2. dc specifications................................................................................................................. .66 9.3. ac specifications................................................................................................................. .66 10. clock scheme ................................................................................................................... .......69 11. package information .........................................................................................................70 12. order information .............................................................................................................. 71 11-0039
pi7c9x7958 pci express? octal uart datasheet page 8 of 71 march 2011 ? revision 1.4 pericom semiconductor table of tables t able 4-1 p in -l ist of 160-p in lfbga .......................................................................................................11 t able 5-1 m ode s election .........................................................................................................................18 t able 5-2 b aud r at e g enerator s etting ................................................................................................23 t able 5-3 s ample b aud r at e s etting .......................................................................................................23 t able 7-1 uart b ase a ddress in i/o m ode .............................................................................................44 t able 7-2 r egisters in i/o m ode ...............................................................................................................45 t able 7-3 uart b ase a ddress in m emory m ode ....................................................................................51 t able 7-4 m emory -m ap mode ....................................................................................................................52 t able 9-1 a bsolute maximum ratings .....................................................................................................66 t able 9-2 dc electrical characteristics ..............................................................................................66 t able 9-3 t ransmitter c haracteristics .................................................................................................66 t able 9-4 r eceiver c haracteristics .......................................................................................................67 t able 10-1 i nput c lock r equirements ....................................................................................................69 list of figures f igure 3-1 pi7c9x7958 b lock d iagram ...................................................................................................10 f igure 5-1 t ransmit and r eceive fifo s ..................................................................................................19 f igure 5-2 i nternal l oopback in pi7c9x7958........................................................................................21 f igure 5-3 c rystal o scillator as the c lock s ource ...........................................................................22 f igure 5-4 e xternal c lock s ource as the c lock s ource ....................................................................22 f igure 7-1 uart r egister b lock a rrangement in i/o m ode ..............................................................44 f igure 7-2 uart r egister b lock a rrangement in m emory m ode ...................................................51 f igure 11-1 p ackage outline drawing .....................................................................................................70 11-0039
pi7c9x7958 pci express? octal uart datasheet page 9 of 71 march 2011 ? revision 1.4 pericom semiconductor 1. features ? x1 pci express link host interface ? eight high performance 950-class uarts ? compliant with pci express base specification 1.1 ? compliant with pci express cem specification 1.1 ? compliant with pci power management 1.2 ? fully 16c550 software compatible uarts ? 128-byte fifo for each transmitter and receiver ? baud rate up to 15 mbps in asynchronous mode ? flexible clock prescaler from 4 to 46 ? automated in-band flow control using programmable xon/xoff in both directions ? automated out-of-band flow control using cts#/rts# and/or dsr#/dtr# ? arbitrary trigger levels for receiver and transmitter fifo interrupts and automatic in-band and out-of-band flow control ? global interrupt status and readable fifo levels to facilitate implementation of efficient device drivers ? detection of bad data in the receiver fifo ? data framing size including 5, 6, 7, 8 and 9 bits ? hardware reconfiguration through microwire compatible eeprom ? operations via i/o or memory mapping ? dual power operation (1.8v for pcie i/o and core, 3.3v for uart i/o) ? power dissipation: 0.9 w typical in normal mode ? industrial temperature range -40 o to 85 o ? 160-pin lfbga package 2. applications ? remote access servers ? network / storage management ? factory automation and process control ? instrumentation ? multi-port rs-232/ rs-422/ rs-485 cards ? point-of-sale systems (pos) ? industrial pc (ipc) ? industrial control ? gaming machines ? building automation ? embedded systems 11-0039
pi7c9x7958 pci express? octal uart datasheet page 10 of 71 march 2011 ? revision 1.4 pericom semiconductor 3. general description the pi7c9x7958 is a pci express octal uart (universal asynchronous receiver-transmitters) i/o bridge. it is specifically designed to meet the latest system requirements of high performance and lead (pb) -free. the bridge can be used in a wide range of applications such as remote access servers, automation, process control, instrumentation, pos, atm and multi-port rs232/ rs422/ rs485 cards. the pi7c9x7958 provides one x1 pcie (dual simplex 2.5 gbps) uplink port, and it is fully compliant with pci express 1.1 and pci power management 1.2 specifications. the bridge supports eight high performance uarts, each of which supports baud rate up to 15 mbps in asynchronous mode. the uarts support in-band and out-band auto flow control, arbitrary trigger level, i/o mapping and memory mapping. the pi7c9x7958 is fully software compatible with 16c550 type device drivers and can be configured to fit the requirements of rs232, rs422 and rs485 applications. the eeprom interface is provided for system implementation convenience. some registers can be pre-programmed via hardware pin settings to facilitate system initialization. for programming flexibility, all of the default configuration registers can be overwritten by eeprom data, such as sub-vendor and sub-system id. pci express interface octal uart interface sout[7:0] sin[7:0] dcd[7:0] dtr[7:0] rts[7:0] cts[7:0] dsr[7:0] ri[7:0] xtlo xtli internal data / command bus txp, txn rxp, rxn clkinp, clkinn rref eeprom interface sr_di sr_cs sr_do sr_clk_o interrupt interface reference clock baud rate generator mod_sel0[3:0] mod_sel1[3:0] mod_sel2[3:0] mod_sel3[3:0] mod_sel0[3:0] mod_sel1[3:0] mod_sel2[3:0] mod_sel3[3:0] figure 3-1 pi7c9x7958 block diagram 11-0039
pi7c9x7958 pci express? octal uart datasheet page 11 of 71 march 2011 ? revision 1.4 pericom semiconductor 4. pin assignment 4.1. pin list of 160-pin lfbga pin name pin name pin name pin name a1 sout[5] c13 sout[3] h1 vtt m3 vddr a2 rts[7] c14 cts[2] h2 vss m4 gpio[2]/deq[3] a3 sout[7] d1 xtlo h3 vss m5 gpio[5]/rxtermadj[0] a4 ri[6] d2 xtli h4 vdda m6 driver_sel0[3]/dtx[0] a5 sin[6] d3 scan_en h11 dsr[0] m7 driver_sel1[2]/dtx[3] a6 dtr[6] d4 cts[5] h12 sin[1] m8 driver_sel2[3] a7 ri[5] d5 dcd[7] h13 sout[1] m9 driver_sel4[0] a8 dsr[5] d6 dtr[7] h14 rts[1] m10 driver_sel5[1] a9 jtg_tdo d7 vss j1 txn m11 vddr a10 dcd[4] d8 dcd[5] j2 txp m12 driver_sel6[2] a11 ri[4] d9 jtg_tms j3 vss m13 driver_sel7[3] a12 sin[4] d10 vss j4 vdda m14 rts[0]/eeprom_bypass a13 sout[4] d11 cts[3] j11 vss n1 perest_l a14 sin[3] d12 vddr j12 ri[0] n2 gpio[0]/deq[1] b1 rts[5] d13 dsr[2] j13 cts[0] n3 vss b2 ri[7] d14 dtr[2] j14 dcd[0] n4 gpio[4]/txtermadj[1] b3 cts[7] e1 sr_cs k1 vddcaux n5 driver_sel0[0]/hi_drv b4 sin[7] e2 sr_di k2 vss n6 driver_sel1[0]/dtx[1] b5 dcd[6] e3 sr_do k3 vddc n7 driver_sel1[3]/deq[0] b6 cts[6] e4 vss k4 vdda n8 driver_sel2[2] b7 rts[6] e11 vss k11 driver_sel7[0] n9 driver_sel3[1] b8 jtg_trst_l e12 rts[3] k12 driver_sel7[2] n10 driver_sel3[3] b9 jtg_tdi e13 sin[2] k13 sout[0] n11 driver_sel5[0] b10 dsr[4] e14 ri[1] k14 sin[0] n12 driver_sel5[3] b11 dtr[4] f1 vddc l1 rxp n13 driver_sel6[0] b12 rts[4] f2 vss l2 rxn n14 driver_sel7[1] b13 ri[3] f3 wakeup_l l3 rref p1 test b14 dcd[2] f4 sr_clk_o l4 vddcaux p2 gpio[1]/deq[2] c1 sin[5] f11 dtr[3] l5 gpio[6]/rxtermadj[1] p3 gpio[3]/txtermadj[0] c2 dtr[5] f12 ri[2] l6 driver_sel0[2]/lo_drv p4 gpio[7]/sr_org c3 vddr f13 dcd[1] l7 vddc p5 driver_sel0[1] c4 dsr[7] f14 dsr[1] l8 vss p6 driver_sel1[1]/dtx[2] c5 vddr g1 clkinp l9 vss p7 driver_sel2[0] c6 dsr[6] g2 clkinn l10 vss p8 driver_sel2[1] c7 sout[6] g3 vddc l11 driver_sel6[1] p9 driver_sel3[0] c8 jtg_tck g4 vdda l12 driver_sel6[3] p10 driver_sel3[2] c9 cts[4] g11 sout[2] l13 vddc p11 driver_sel4[1] c10 vddc g12 rts[2] l14 dtr[0] p12 driver_sel4[2] c11 dcd[3] g13 cts[1] m1 vss p13 driver_sel4[3] c12 dsr[3] g14 dtr[1] m2 vss p14 driver_sel5[2] table 4-1 pin-list of 160-pin lfbga 11-0039
pi7c9x7958 pci express? octal uart datasheet page 12 of 71 march 2011 ? revision 1.4 pericom semiconductor 4.2. pin description 4.2.1. uart interface pin no. name type description uart interface a3, c7, a1, a13, c13, g11, h13, k13 sout [7:0] o uart serial data outputs: the output pins transmit serial data packets with start and end bits. sout[0] and sout[1] are output signals with weak internal pull-down resistors. b4, a5, c1, a12, a14, e13, h12, k14 sin [7:0] i uart serial data inputs: the input pins receive serial data packets with start and end bits. the pins are idle high. d5, b5, d8, a10, c11, b14, f13, j14 dcd [7:0] i modem data-carrier-detect input and general purpose input (active low) d6, a6, c2, b11, f11, d14, g14, *l14 dtr [7:0] o modem data-terminal-read y output (active low): if automated dtr# flow control is en abled, the dtr# pin is asserted and deasserted if the receiver fifo reaches or falls below the programmed thresholds, respectively. dtr[0] and dtr[1] are output signals with weak in ternal pull-down resistors. a2, b7, b1, b12, e12, g12, h14, *m14 rts [7:0] o modem request-to-send output (active low): if automated rts# flow control is enabled, the rts# pin is deasserted and reasserted whenever the receiver fifo reaches or falls below the programmed thresholds, respectively. rts[0] and rts[1] are output signals with weak internal pull-down resistors. eeprom bypass: during system initialization, rts[0] acts as the eeprom bypass pin, and it is used to bypass eeprom pre-loading. the pin is active-high. when it is asserted at start-up, the eeprom pre-loading is bypassed, and no configuration data is loaded from the eeprpom. otherwis e, configuration data is loaded from the eeprom. b3, b6, d4, c9, d11, c14, g13, j13 cts [7:0] i modem clear-to-send input (active low): if automated cts# flow control is enabled, upon deassertion of the cts# pin, the transmitter will complete the curr ent character and enter the idle mode until the cts# pin is reassert ed. note: flow control characters are transmitted regardless of the state of the cts# pin. c4, c6, a8, b10, c12, d13, f14, h11 dsr [7:0] i modem data-set-ready input (active low): if automated dsr# flow control is enabled, upo n deassertion of the dsr# pin, the transmitter will complete the curr ent character and enter the idle mode until the dsr# pin is reassert ed. note: flow control characters are transmitted regardless of the state of the dsr# pin. b2, a4, a7, a11, b13, f12, e14, j12 ri [7:0] i modem ring-indicator input (active low) d1 xtlo o crystal oscillator output d2 xtli i crystal oscillator input or external clock pin: the maximum frequency supported by this device is 60mhz. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 13 of 71 march 2011 ? revision 1.4 pericom semiconductor pin no. name type description *m6, *l6, p5, *n5 driver_sel0 [3:0] o driver_sel0: used to select rs-232/ rs-424/ 4-wire rs-485/ 2-wire rs-458 serial port mode for uart 0. driver_sel0 [3:0] are output signals with weak internal pull-down resistors. driver current level control (dtx[0]): during system initialization, driver_sel0[3] acts as the dtx[0] pin, and it is used to control the driver current le vel. by default, it is set to ?0? without pin strapped. low driver control (lo_drv): during system initialization, driver_sel0[2] acts as the lo_drv pin, and it is used to decrease the nominal value of the pci express lane?s driver current level. by default, it is se t to ?0? without pin strapped. high driver control (hi_drv): during system initialization, driver_sel0[0] acts as the hi_drv pin, and it is used to increase the nominal value of the pci express lane?s driver current level. by default, it is set ?0? without pin strapped. *n7, *m7, *p6, *n6 driver_sel1 [3:0] o driver_sel1: used to select rs-232/ rs-424/ 4-wire rs-485/ 2-wire rs-458 serial port mode for uart 1. driver_sel1 [3:0] are output signals with weak internal pull-down resistors. driver equalization level control (deq[0]): during system initialization, driver_sel1[3] acts as the deq[0] pin, and it is used to control the driver current le vel. by default, it is set to ?0? without pin strapped. driver current level control (dtx[3:1]): during system initialization, driver_sel1[2:0] ac ts as the dtx[3:1] pins, and they are used to control the driver current level. by default, they are set to ?000? without pin strapped. m8, n8, p8, p7 driver_sel2 [3:0] o driver_sel2: used to select rs-232/ rs-424/ 4-wire rs-485/ 2-wire rs-458 serial port mode for uart 2. driver_sel2[3] is an output signal with a weak internal pull-up resistor, and other driver_sel2 signals are output signals with internal pull-down resistors. n10, p10, n9, p9 driver_sel3 [3:0] o driver_sel3: used to select rs-232/ rs-424/ 4-wire rs-485/ 2-wire rs-458 serial port mode for uart 3. driver_sel3 [3:0] are output signals with weak internal pull-up resistors. p13, p12, p11, m9 driver_sel4 [3:0] o driver_sel4: used to select rs-232/ rs-424/ 4-wire rs-485/ 2-wire rs-458 serial port mode for uart 4. driver_sel4 [3:0] are output signals with weak internal pull-up resistors. n12, p14, m10, n11 driver_sel5 [3:0] o driver_sel5: used to select rs-232/ rs-424/ 4-wire rs-485/ 2-wire rs-458 serial port mode for uart 5. driver_sel5 [3:0] are output signals with weak internal pull-up resistors. l12, m12, l11, n13 driver_sel6 [3:0] o driver_sel6: used to select rs-232/ rs-424/ 4-wire rs-485/ 2-wire rs-458 serial port mode for uart 6. driver_sel6 [3:0] are output signals with weak internal pull-up resistors. m13, k12, n14, k11 driver_sel7 [3:0] o driver_sel7: used to select rs-232/ rs-424/ 4-wire rs-485/ 2-wire rs-458 serial port mode for uart 7. driver_sel7 [3:0] are output signals with weak internal pull-up resistors. 4.2.2. pci express interface pin no. name type description pci express interface j2, j1 txp, txn o pci express serial output signal: differential pci express output signals. l1, l2 rxp, rxn i pci express serial input signal: differential pci express input signals. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 14 of 71 march 2011 ? revision 1.4 pericom semiconductor pin no. name type description g1, g2 clkinp, clkinn i reference input clock: connects to external 100mhz differential clock the input clock signals must be delivered to the clock buffer cell through an ac-coupled interface so that only the ac information of the clock is received, converted, and buffered. it is recommended that a 0.1uf be used in the ac-coupling. l3 rref i reference resistor: to accurately set internal bias references, a precision resistor must be connected between rref and vss . the resistor should have a nominal value of 2.1 k ? and accuracy of +/- 1% 4.2.3. system interface pin no. name type description system interface n1 perest_l i system reset input *p4, *l5, *m5, *n4, *p3, *m4, *p2, *n2 gpio [7:0] i/o general-purpose bi-direction signals: these eight general-purpose pins are programmed as either input-only or bi-directional pins by writing the gpio output enable control register. gpio[2] is a bi-directiona l signal with a weak internal pull-up resistor, and other gpio pins are bi-directional signals with weak internal pull-down resistors. eeprom organization pin (sr_org): during system initialization, gpio[7] acts as th e sr_org pin, and it is used to select the organization structure of the eeprom. the pin is active-high. when it is asserted at start-up, the eeprom configuration data is organized in 16-bit structure. otherwise, 8-bit structure is used. receiver termination adjustment (rxtermadj[1:0]): during system initialization, gpio[6:5] ac ts as the rxtermadj[1:0] pins, and they are used to adjust the rece ive termination resistor value. by default, they are set to ?00? without pin strapped. transmit termination adjustment (txtermadj[1:0]): during system initialization, gpio[4:3] acts as the txtermadj[1:0] pins, and they are used to adjust the transmit termination resistor value. by default, they are set to ?00? without pin strapped. driver equalization level control (deq[3:1]): during system initialization, gpio[2:0] acts as the deq[3:1] pins, and they are used to control the driver current le vel. by default, they are set to ?100? without pin strapped. f3 wakeup_l o wakeup signal (active low): when the ring indicator is received on uart channel 0 in l2 state, the wakeup_l is asserted. wakeup_l is an output signal with a weak internal pull-down resistor. 4.2.4. test signals pin no. name type description test signals b9 jtg_tdi i test data input: when scan_en is high, the pin is used (in conjunction with tck) to shift data and instructions into the tap in a serial bit stream. jtg_tdi is an input signal with a weak internal pull-up resistor. a9 jtg_tdo o test data output: when scan_en is high, it is used (in conjunction with tck) to shift data out of the test access port (tap) in a serial bit stream 11-0039
pi7c9x7958 pci express? octal uart datasheet page 15 of 71 march 2011 ? revision 1.4 pericom semiconductor pin no. name type description d9 jtg_tms i test mode select: used to control the state of the test access port controller. jtg_tms is an input signal with a weak internal pull-up resistor. c8 jtg_tck i te st clock: used to clock state information and data into and out of the chip during boundary scan. b8 jtg_trst_l i test reset: active low signal to reset the tap controller into an initialized state. jtg_trst_l is an input signal with a weak internal pull-up resistor. p1 test i this input signal should be tied to ground during normal operation. d3 scan_en i scan test enable pin: scan_en is an input signal with a weak internal pull-up resistor. 4.2.5. eeprom interface pin no. name type description eeprom interface e1 sr_cs o eeprom chip select: sr_cs is an output signal with a weak internal pull-up resistor. e2 sr_di i eeprom data input: serial data input interface to the eeprom. sr_di is an input signal with a weak internal pull-up resistor. e3 sr_do o eeprom data output: serial data output interface to the eeprom. sr_do is an output signa l with a weak internal pull-up resistor. f4 sr_clk_o o eeprom clock output. 4.2.6. power pins pin no. name type description power pins c10, f1, g3, k3, l7, l13 vddc p 1.8 v power pin: used as digital core power pins. g4, h4, j4, k4 vdda p 1.8 v power pin: used as analog core power pins. c3, c5, d12, m3, m11 vddr p 3.3 v power pin: used as digital i/o power pins. k1, l4 vddcaux p 1.8 v power pin: used as auxiliary power pins. h1 vtt p 1.8v termination voltage: provides driver termination voltage at transmitter. should be given the same considera tion as vddcaux. d7, d10, e4, e11, f2, h2, h3, j3, j11, k2, l8, l9, l10, m1, m2, n3 vss p ground pin: used as ground pins. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 16 of 71 march 2011 ? revision 1.4 pericom semiconductor 5. functional description the pi7c9x7958 is an integrated solution of eight high-performance 16c550 uarts with one x1 pci express host interface. the pci express host interface is compliant with the pci express base specification 1.1, pci express cem specification 1.1, and pci power management 1.2. in addition, the chip is compliant with the advanced configuration power interface (acpi) specification and the pci standard hot-plug controller (shpc) and subsystem specification revision 1.0. the x1 pci express host interface supports up to 2.5 gbps bandwidth and complete pci express configuration register set. the pci express interface allows direct access to the configuration and status registers of the uart channels. the uarts in the pi7c9x7958 support the complete register set of the 16c550-type devices. the uarts support baud rates up to 15 mbps in asynchronous mode. each uart channel has 128-byte deep transmit and receive fifos. the high-speed fifos reduce cpu utilization and improve data throughput. in addition, the uarts support enhanced features including automated in-band flow control using programmable xon/ xoff in both directions, automated out-band flow control using cts#/ rts# and/or drs#/ dtr#, and arbitrary transmit and receive trigger levels. 5.1. configuration space the pi7c9x7958 has two sets of registers to allow various configuration and status monitoring functions. the pci express configuration space registers enable the plug-and-play and auto-configuration when the device is connected to the pci express system bus. the uart configuration and internal registers enable the general uart operation functions, status control and monitoring. 5.1.1. pci express configuration space the pi7c9x7958 is recognized as a pci express endpoint, which is mapped into the configuration space as a single logical device. each endpoint in the system, including the pi7c9x7958, is part of a hierarchy domains originated by the root complex, which is a tree with a root port at its head in the configuration space. the device configuration registers are implemented for the user to access the functionalities provided by the pci express specification. the specification utilizes a flat memory-mapped configuration space to access device configuration registers. all pci express endpoints facilitate a pci-compatible configuration space to maintain compatibility with pci software configuration mechanism. pci local bus specification, revision 3.0 allocates 256 bytes per device function. pci express base specification 1.1 extends the configuration space to 4096 bytes to allow enhanced features. the first 256 bytes of the pci express configuration space are pci 3.0 compatible region, and the rest of the 4096 bytes are pci express configuration space. the user can access the pci 3.0 compatible region either by conventional pci 3.0 configuration addresses or by the pci express memory-mapping addresses. these two types of accesses to the pci 3.0 compatible region have identical results. the enhanced features in the pci express configuration space can only be accessed by pci express memory-mapping accesses. 5.1.2. uart configuration space through the uart registers, the user can control and monitor various functionalities of the uarts on the pi7c9x7958 including fifos, interrupt status, line status, modem status and sample clock. each of the uart?s transmit and receive data fifos can be conveniently accessed by reading and writing the registers in the uart configuration space. these registers allow flexible programming capability and versatile device operations of the pi7c9x7958. each uart is accessed through an 8-byte i/o blocks. the addresses 11-0039
pi7c9x7958 pci express? octal uart datasheet page 17 of 71 march 2011 ? revision 1.4 pericom semiconductor of the uart blocks are offset by the base address referred by the base address register (bar). the value of the base address is loaded from the i/o or memory base address defined in the pci express configuration space. the pi7c9x7958 also supports enhanced features such as xon/xoff, automatic flow control, baud rate prescaling and various status monitoring. these enhanced features are available through the memory address offset by the bar in the pci express configuration space. the basic features available in the registers in i/o mode are also available in the registers in memory-mapping mode. accesses to these registers are equivalent in these two modes. the uarts on the pi7c9x7958 supports operations in 16c450, 16c550 and 16c950 modes. these modes of operation are selected by writing the sfr, fcr and efr registers. the pi7c9x7958 is backward compatible with these modes of operation. 5.2. device operation the pi7c9x7958 is configured by the root complex in the bootstrap process during system start-up. the root complex performs bus scans and recognizes the device by reading vendor and device ids. upon successful device identification, the system then loads device-specific driver software and allocates i/o, memory and interrupt resources. the driver software allows the user to access the functions of the device by reading and writing the uart registers. the pci express interface incorporates convenient device operation and high system performance. 5.2.1. configuration access the pi7c9x7958 accepts type 0 configuration read and write accesses defined in the pci express base1.1 specification. the first 256 bytes of the pci express configuration are compatible with pci 3.0. 5.2.2. i/o reads/writes the pci express interface of the pi7c9x7958 decodes incoming transaction packets. if the address is within the region assigned by the i/o base address registers, the transaction is recognized as an i/o read or write. 5.2.3. memory reads/writes similar to the i/o read/write, if the address of the transaction packet is within the memory range, a memory read/write occurs. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 18 of 71 march 2011 ? revision 1.4 pericom semiconductor 5.2.4. mode selection all of the internal uart channels in the i/o bridge support the 16c450, 16c550, enhanced 16c550, and enhanced 950 uart modes. the mode of the uart operation is selected by toggling the special function register (sfr[5]) and enhanced function register (efr[4]). the fifo depth of each mode and the mode selection is tabulated in the table below. table 5-1 mode selection uart mode sfr[5] efr[4] fifo size 450/550 x 0 1/16 enhanced 550 0 1 128 enhanced 950 1 1 128 5.2.5. 450/550 mode the 450 mode is inherently supported when 550 mode is selected. when in the 450 mode, the fifos are in the ?byte mode?, which refers to the one-byte buffer in the transmit holding register and the receive holding register in each of the uart channels. when in the 550 mode, the uarts support an increased fifo depth of 16. when efr[4] is set to ?0?, the sfr[5] is ignored, and the 450/550 mode is selected. 5.2.6. enhanced 550 mode setting the sfr[5] to ?0? and efr[4] to ?1? enables the enhanced 550 mode. the enhanced 550 mode further increases fifo depth to 128. 5.2.7. enhanced 950 mode 128-deep fifos are supported in the enhanced 950 mode. when the enhanced 950 mode is enabled, the uart channels support additional features: ? sleep mode ? special character detection ? automatic in-band flow control ? automatic flow control using selectable arbitrary thresholds ? readable status for automatic in-band and out-of-band flow control ? flexible clock prescaler ? programmable sample clock ? dsr/dtr automatic flow control 5.2.8. transmit and receive fifos each channel of the uarts consists of 128 bytes of transmit fifos and 128 bytes of receive fifos, namely the transmit holding registers (thr) and the receive holding registers (rhr). the fifos provide storage space for the data before they can be transmitted or processed. the thr and rhr operate simultaneously to transmit and read data. the transmitter reads data from the thr into the transmit shift register (tsr) and removes the data from top of the thr. it then converts the data into serial format with start and stop bits and parity bits if required. if the transmitter completes transmitting the data in the tsr and the thr is empty, the transmitter is in the idle state. the data that arrive most recently are written to the bottom of the thr. if the thr is full, and the user attempts to write data to the thr, a data overrun occurs and the data is lost. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 19 of 71 march 2011 ? revision 1.4 pericom semiconductor the receiver writes data to the bottom of the rhr when it finishes receiving and decoding the data bits. if the rhr is full when the receiver attempts to write data to it, a data overrun occurs. any read operation to an empty rhr is invalid. the empty and full status of the thr and rhr can be determined by reading the empty and full flags in the line status register (lsr). when the transmitter and receiver are ready to transfer data to and from the fifos, interrupts are raised to signal this condition. additionally, the user can use the receive fifo data counter (rfdc) and transmit fifo data counter (tfdc) registers to determine the number of items in each fifo. data0 data1 data2 uart common mode address pci express master rhr lsr thr data125 data126 data127 lsr0 lsr1 lsr2 lsr125 lsr126 lsr127 data0 data1 data2 data125 data126 data127 rp wp rp wp figure 5-1 transmit and receive fifos 11-0039
pi7c9x7958 pci express? octal uart datasheet page 20 of 71 march 2011 ? revision 1.4 pericom semiconductor 5.2.9. automated flow control the device uses automatic in-band flow control to prevent data-overrun to the local receive fifo and remote receive fifo. this feature works in conjunction with the special character detection. when an xoff condition is detected, the uart transmitter will suspend any further data transmission after the current character transmission is completed. the transmitter will resume data-transmission as soon as an xon condition is detected. the automatic in-band feature is enabled by the enhanced function register (efr). efr[1:0] enables the in-band receive flow control, and efr[3:2] enables the in-band transmit flow control. the out-of-band flow control utilizes rts# and cts# pins to suspend and resume the data transmission and to prevent data-overrun. an asserted cts# pin signals the uart to suspend transmission due to a full remote receive fifo. upon detecting an asserted cts# pin, the uart will complete the current character transmission and enters idle mode until the cts# pin is deasserted. the uart deasserts rts# to signal the remote transmitter that the local receive fifo reaches the programmed upper trigger level. when the local receive fifo falls below the programmed lower trigger level, the rts# is reasserted. the automatic out-of-band flow control is enabled by efr[7:6]. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 21 of 71 march 2011 ? revision 1.4 pericom semiconductor 5.2.10. internal loopback the internal loopback capability of the uarts is enabled by setting modem control register bit-4 (mcr[4]) to 1. when the feature is enabled, the data from the output of the transmit shift register are looped back to the input of the receive shift register. this feature provides the users a way to perform system diagnostics by allowing the uart to receive the same data it is sending. internal bus lines and control signals transmit shift register receive shift register vcc mcr bit-4=1 vcc vcc modem / general purpose control logic rts# cts# dtr# dsr# tx[7:0] rx[7:0] rts#[7:0] cts#[7:0] dtr#[7:0] dsr#[7:0] figure 5-2 internal loopback in pi7c9x7958 11-0039
pi7c9x7958 pci express? octal uart datasheet page 22 of 71 march 2011 ? revision 1.4 pericom semiconductor 5.2.11. crystal oscillator the pi7c9x7958 uses a crystal oscillator or an external clock source to provide system clock to the baud rate generator. when a clock source is used, the clock signal should be connected to the xtli pin, and a 2k pull-up resistor should be connected to the xtlo pin. when a crystal oscillator is used, the xtli is the input and xtlo is the output, and the crystal should be connected in parallel with two capacitors. r 14.7456 mhz xtli xtlo c1 c2 figure 5-3 crystal oscillator as the clock source xtli xtlo r1 2k vcc external clock gnd vcc figure 5-4 external clock source as the clock source 11-0039
pi7c9x7958 pci express? octal uart datasheet page 23 of 71 march 2011 ? revision 1.4 pericom semiconductor escaler divisor ency inputfrequ baudrate pr * ? baud rate generation the built-in baud rate generator (brg) allows a wide range of input frequency and flexible baud rate generation. to obtain the desired baud rate, the user can set the sample clock register (scr), divisor latch low register (dll), divisor latch high register (dlh) and clock prescale registers (cprm and cprn). the baud rate is generated according to the following equation: the parameters in the equation above can be programmed by setting the ?scr?, ?dll?, ?dlh?, ?cprm? and ?cprn? registers according to the table below. table 5-2 baud rate generator setting setting description divisor dll + (256 * dlh) prescaler ) k samplecloc ( * 2 1 n m ? ? sampleclock scr ? 16 , (scr = ?0h? to ?ch?) m cprm, (cprm = ?01h? to ?02h?) n cprn, (cprn = ?0h? to ?7h?) to ensure the proper operation of the baud rate generator, users should avoid setting the value ?0? to sample clock, divisor and prescaler. the following table lists some of the commonly used baud rates and the register settings that generate a specific baud rate. the examples assume an input clock frequency of 14.7456 mhz. the scr register is set to ?0h?, and the cprm and cprn registers are set to ?1h? and ?0h? respectively. in these examples, the baud rates can be generated by different combination of the dlh and dll register values. table 5-3 sample baud rate setting baud rate dlh dll 1,200 3h 00h 2,400 1h 80h 4,800 0h c0h 9,600 0h 60h 19,200 0h 30h 28,800 0h 20h 38,400 0h 18h 57,600 0h 10h 115,200 0h 08h 921,600 0h 01h 5.2.13. power management the pi7c9x7958 supports the d0, d1, d2 and d3 power states. the device is compliant with pci power management specification revision 1.2. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 24 of 71 march 2011 ? revision 1.4 pericom semiconductor 6. pci express regist er description 6.1. register types register type definition hwint hardware initialization ro read only wo write only rw read / write rwc read / write 1 to clear rwcs sticky - read only / write 1 to clear rws sticky - read / write 6.2. configuration registers the following table details the allocation of the register fields of the pci 2.3 compatible type 0 configuration space header. 31 ? 24 23 ? 16 15 ? 8 7 ? 0 byte offset device id vendor id 00h status command 04h class code revision id 08h reserved header type master latency timer cache line size 0ch base address register 0 10h base address register 1 14h reserved 18h~28h subsystem id subsystem vendor id 2ch reserved 30h capability pointer 34h reserved 38h reserved interrupt pin interrupt line 3ch reserved 40h ? 7fh power management capabilities next id = 8c capability id = 01 80h pm data ppb support power management data 84h message control register next id =9c capability id = 05 8ch message address register 90h message upper address register 94h message data register 98h vpd register next id = a4 capability id = 03 9ch vpd data register a0h vendor define register(28h) next id = e0 capability id = 09 a4h xpip csr0 a8h xpip csr1 ach ack latency timer replay time-out counter b0h uart driver selection b4h power management control parameter b8h debug register bch ? c4h phy parameter c8h reserved cch ? d4h gpio data and control d8h eeprom data eeprom control dch pci express capability register next id = 00h capability id = 10 e0h device capability e4h device status device control e8h link capability ech link status link control f0h 11-0039
pi7c9x7958 pci express? octal uart datasheet page 25 of 71 march 2011 ? revision 1.4 pericom semiconductor 31 ? 24 23 ? 16 15 ? 8 7 ? 0 byte offset reserved f4h - fch other than the pci 2.3 compatible configuration space header, the i/o bridge also implements pci express extended configuration space header, which includes advanced error reporting registers. the following table details the allocation of the register fields of pci express extended capability space header. the first extended capability always begins at offset 100h with a pci express enhanced capability header and the rest of capabilities are located at an offset greater than 0ffh relative to the beginning of pci compatible configuration space. 31 ? 24 23 ? 16 15 ? 8 7 ? 0 byte offset next capability offset = 000h capability version pci expr ess extended capability id = 001h 100h uncorrectable error status register 104h uncorrectable error mask register 108h uncorrectable error severity register 10ch correctable error status register 110h correctable error mask register 114h advanced error capabilities and control register 118h header log register 11ch~128h 6.2.1. vendor id register ? offset 00h bit function type description 15:0 vendor id ro identifies pericom as the vendor of this i/o bridge. the default value may be changed by auto-loading from eeprom. reset to 12d8h. 6.2.2. device id register ? offset 00h bit function type description 31:16 device id ro identifies this i/o bridge as the pi7c9x7958. the default value may be changed by auto-loading from eeprom. reset to 7958h. 6.2.3. command register ? offset 04h bit function type description 0 i/o space enable rw controls a device?s response to i/o space accesses. a value of 0 disables the device response. a value of 1 allows the device to respond to i/o space accesses. reset to 0b. 1 memory space enable rw controls a device?s response to memory space accesses. a value of 0 disables the device response. a value of 1 allows the device to response to memory space accesses. reset to 0b. 2 bus master enable ro it is not implemented. hardwired to 0b. 3 special cycle enable ro does not apply to pci express. must be hardwired to 0b. 4 memory write and invalidate enable ro does not apply to pci express. must be hardwired to 0b. 5 vga palette snoop enable ro does not apply to pci express. must be hardwired to 0b. 6 parity error response enable rw controls the device?s response to pa rity errors. when the bit is set, the device must take its normal action when a parity error is detected. when the bit is 0, the devi ce sets its detected parity error status bit when an error is detected. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 26 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description reset to 0b. 7 wait cycle control ro does not apply to pci express. must be hardwired to 0b. 8 serr# enable rw this bit, when set, enables repor ting of non-fatal and fatal errors detected by the device to the root complex. reset to 0b. 9 fast back-to-back enable ro does not apply to pci express. must be hardwired to 0b. 10 interrupt disable rw controls the ability of the i/o brid ge to generate intx interrupt messages. reset to 0b. 15:11 reserved ro reset to 00000b. 6.2.4. status register ? offset 04h bit function type description 18:16 reserved ro reset to 000b. 19 interrupt status ro indicates that an intx interrupt me ssage is pending internally to the device. reset to 0b. 20 capabilities list ro set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure) reset to 1b. 21 66mhz capable ro does not apply to pci express. must be hardwired to 0b. 22 reserved ro reset to 0b. 23 fast back-to-back capable ro does not apply to pci express. must be hardwired to 0b. 24 master data parity error rwc it is not implemented. hardwired to 0b. 26:25 devsel# timing ro does not apply to pci express. must be hardwired to 0b. 27 signaled target abort rwc set to 1 (by a completer) whenever completing a request in the i/o bridge side using completer abort completion status. reset to 0b. 28 received target abort rwc it is not implemented. hardwired to 0b. 29 received master abort rwc it is not implemented. hardwired to 0b. 30 signaled system error rwc set to 1 when the i/o bridge sends an err_fatal or err_nonfatal message, and the serr enable bit in the command register is 1. reset to 0b. 31 detected parity error rwc set to 1 whenever the i/o brid ge receives a poisoned tlp. reset to 0b. 6.2.5. revision id register ? offset 08h bit function type description 7:0 revision ro indicates revision number of the i/o bridge. the default value may be changed by auto-loading from eeprom. reset to 00h. 6.2.6. class code register ? offset 08h 11-0039
pi7c9x7958 pci express? octal uart datasheet page 27 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 15:8 programming interface ro read as 02h to indicate no programming interfaces have been defined for pci-to-pci bridges 23:16 sub-class code ro read as 00h to indicate device is pci-to-pci bridge 31:24 base class code ro read as 07h to indicate device is a bridge device 6.2.7. cache line register ? offset 0ch bit function type description 7:0 cache line size rw the cache line size register is set by the system firmware and the operating system to system cache line size. this field is implemented by pci express devices as a rw field for legacy compatibility purposes but has no impact on any pci express device functionality. reset to 00h. 6.2.8. master latency timer register ? offset 0ch bit function type description 15:8 latency timer ro does not apply to pci express. must be hardwired to 00h. 6.2.9. header type register ? offset 0ch bit function type description 23:16 header type ro read as 00h to indicate that the register layout conforms to the standard pci-to-pci bridge layout. 6.2.10. base address register 0 ? offset 10h bit function type description 31:0 base address 0 rw use this i/o base address to map the uart 16550 compatible registers. the base address can be allocated to 64 bytes. reset to 00000001h. 6.2.11. base address register 1 ? offset 14h bit function type description 31:0 base address 1 rw use this memory base address to map the uart 16550 compatible and enhanced registers. the base address can be allocated to 4096 bytes. reset to 00000000h 6.2.12. subsystem vendor register ? offset 2ch bit function type description 15:0 sub vendor id ro indicates the sub-system vendor id. the default value may be changed by auto-loading from eeprom. reset to 0000h. 6.2.13. subsystem id register ? offset 2ch bit function type description 31:16 sub system id ro indicates the sub-system device id. the default value may be changed by auto-loading from eeprom. reset to 0000h. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 28 of 71 march 2011 ? revision 1.4 pericom semiconductor 6.2.14. capabilities pointer register ? offset 34h bit function type description 7:0 capabilities pointer ro this optional register points to a linked list of new capabilities implemented by the device. this default value may be changed by auto-loading from eeprom. the default value is 80h. 6.2.15. interrupt line register ? offset 3ch bit function type description 7:0 interrupt line rw used to communicate interrupt line routing information. post software will write the routing inform ation into this register as it initializes and configures the system. reset to 00h. 6.2.16. interrupt pin register ? offset 3ch bit function type description 15:8 interrupt pin ro identifies the legacy interrup t message(s) the device uses. reset to 01h. 6.2.17. power management capability id register ? offset 80h bit function type description 7:0 enhanced capabilities id ro read as 01h to indicate that th ese are power management enhanced capability registers. 6.2.18. next item pointer register ? offset 80h bit function type description 15:8 next item pointer ro the pointer points to the power management capability register (8ch). reset to 8ch. 6.2.19. power management capabilities register ? offset 80h bit function type description 18:16 power management revision ro read as 011b to indicate the i/o bridge is compliant to revision 1.1 of pci power management in terface specifications. 19 pme# clock ro does not apply to pci express. must be hardwired to 0b. 20 auxiliary power ro read as 1b to indicate the i/o br idge forwards the pme# message in d3cold and an auxiliary power source is required. 21 device specific initialization ro read as 0b to indicate the i/o bridge does not have device specific initialization requirements. the de fault value may be changed by auto-loading from eeprom. 24:22 aux current ro reset as 111b to indicate the i/o bridge need 375 ma in d3 state. the default value may be changed by auto-loading from eeprom. 25 d1 power state support ro read as 1b to indicate the i/o bridge supports the d1 power management state. the default value may be changed by auto-loading from eeprom. 26 d2 power state support ro read as 1b to indicate the i/o bridge supports the d2 power management state. the default value may be changed by auto-loading from eeprom. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 29 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 31:27 pme# support ro read as 01000b to indicate the i/o bridge supports the forwarding of pme# message in all power states. the default value may be changed by auto-loading from eeprom. 6.2.20. power management data register ? offset 84h bit function type description 1:0 power state rw indicates the current power state of the i/o bridge. writing a value of d0 causes a hot reset without asserting perest_l when the previous state was d3. 00b: d0 state 01b: d1 state 10b: d2 state 11b: d3 hot state reset to 00b. 2 reserved ro read as 0b. 3 no_soft_reset ro when set, this bit indicates that i/o bridge transitioning from d3hot to d0 does not perform an internal reset. when clear, an internal reset is performed when power state transits from d3hot to d0. the default value may be changed by auto-loading from eeprom. reset to 0b. 7:4 reserved ro read as 0h. 8 pme# enable rw when asserted, the i/o bridge w ill generate the pme# message. reset to 0b. 12:9 data select rw select data registers. reset to 0h. 14:13 data scale ro read as 00b. 15 pme status ro indicates that the pme# message is pending internally to the i/o bridge. reset to 0b. 6.2.21. ppb support extensions ? offset 84h bit function type description 21:16 reserved ro reset to 000000b. 22 b2_b3 support for d3 hot ro does not apply to pci express. must be hardwired to 0b. 23 bus power / clock control enable ro does not apply to pci express. must be hardwired to 0b. 6.2.22. pm data register ? offset 84h bit function type description 31:24 pm data register ro pm data register. reset to 00h 6.2.23. message signaled interrupts (msi) capability id register 8ch bit function type description 7:0 enhanced capability id ro read as 05h to indicate that th is is message signaled interrupt capability register. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 30 of 71 march 2011 ? revision 1.4 pericom semiconductor 6.2.24. message signaled interrupts (msi) next item pointer 8ch bit function type description 15:8 next item pointer ro the pointer points to the vendor sp ecific capability register (9ch). reset to 9ch. 6.2.25. message address register ? offset 90h bit function type description 1:0 reserved ro reset to 00b. 31:2 message address rw if the message enable bit is set, th e contents of this register specify the dword aligned address for msi memory write transaction. reset to 0. 6.2.26. message upper address register ? offset 94h bit function type description 31:0 message upper address rw this register is only effective if the device supports a 64-bit message address is set. reset to 00000000h. 6.2.27. message data register ? offset 98h bit function type description 15:0 message data rw reset to 0000h. 6.2.28. vpd capability id register ? offset 9ch bit function type description 7:0 enhanced capabilities id ro read as 03h to indicate that these are vpd enhanced capability registers. 6.2.29. next item pointer register ? offset 9ch bit function type description 15:8 next item pointer ro the pointer points to the vpd capability register (a4h). reset to a4h 6.2.30. vpd register ? offset 9ch bit function type description 16 vpd start rw starts vpd read or write cycle. assert by software and is de-asserted by hardware. reset to 0b. 17 vpd operation rw 0b: performs vpd read command to vpd table at the location as specified in vpd address 1b: performs vpd write command to vpd table at the location as specified in vpd address reset to 0b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 31 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 22:18 vpd address rw contains dword address that is used to generate read or write cycle to the vpd table stored in eeprom. reset to 00000b. 31:23 reserved ro read as 000h. 6.2.31. vpd data register ? offset a0h bit function type description 31:0 vpd data rw when read, it returns the last da ta read from vpd table at the location as specifie d in vpd address. when writes, it places the current data into vpd table at the location as specified in vpd address. reset to 00000000h. 6.2.32. vendor specific capability id register ? offset a4h bit function type description 7:0 enhanced capabilities id ro read as 09h to indicate that these are vendor specific capability registers. 6.2.33. next item pointer register ? offset a4h bit function type description 15:8 next item pointer ro the pointer points to the pci e xpress capability register (e0h). reset to e0h. 6.2.34. length register ? offset a4h bit function type description 31:16 length information ro the length field provides the information for number of bytes in the capability structure (including the id and next pointer bytes). reset to 28h. 6.2.35. xpip csr0 ? offset a8h (test purpose only) bit function type description 31:0 reserved rw reset to 04001060h. 6.2.36. xpip csr1 ? offset ach (test purpose only) bit function type description 31:0 reserved rw reset to 004000271h. 6.2.37. replay time-out counter ? offset b0h bit function type description 11:0 user replay timer rw a 12-bit register contains a user-defined value. the default value may be changed by auto-loading from eeprom. reset to 000h. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 32 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 12 enable user replay timer rw when asserted, the user-defined replay time-out value would be employed. the default value may be changed by auto-loading from eeprom. reset to 0b. 15:13 reserved ro reset to 000b. 6.2.38. acknowledge latency timer ? offset b0h bit function type description 29:16 user ack latency timer rw a 14-bit register contains a user-defined value. the default value may be changed by auto-loading from eeprom. reset to 0000h.. 30 enable user ack latency rw when asserted, the user-defined ack latency value would be employed. the default value may be changed by auto-loading from eeprom. reset to 0b. 31 reserved ro reset to 0b. 6.2.39. uart driver setting ? offset b4h bit function type description 3:0 uart 0 transmitter driver enable rw uart 0 driver. the default value may be changed by auto-loading from eeprom. 0000b: rs232 0001b: rs422 1011b: rs485-4w 1111b: rs485-2w reset to 0000b. 7:4 uart 1 transmitter driver enable rw uart 1 driver. the default value may be changed by auto-loading from eeprom. 0000b: rs232 0001b: rs422 1011b: rs485-4w 1111b: rs485-2w reset to 0000b. 11:8 uart 2 transmitter driver enable rw uart 2 driver. the default value may be changed by auto-loading from eeprom. 0000b: rs232 0001b: rs422 1011b: rs485-4w 1111b: rs485-2w reset to 0000b. 15:12 uart 3 transmitter driver enable rw uart 3 driver. the default value may be changed by auto-loading from eeprom. 0000b: rs232 0001b: rs422 1011b: rs485-4w 1111b: rs485-2w reset to 0000b. 19:16 uart 4 transmitter driver rw uart 4 driver. the default value may be changed by auto-loading from eeprom. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 33 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description enable 0000b: rs232 0001b: rs422 1011b: rs485-4w 1111b: rs485-2w reset to 0000b. 23:20 uart 5 transmitter driver enable rw uart 5 driver. the default value may be changed by auto-loading from eeprom. 0000b: rs232 0001b: rs422 1011b: rs485-4w 1111b: rs485-2w reset to 0000b. 27:24 uart 6 transmitter driver enable rw uart 6 driver. the default value may be changed by auto-loading from eeprom. 0000b: rs232 0001b: rs422 1011b: rs485-4w 1111b: rs485-2w reset to 0000b. 31:28 uart 7 transmitter driver enable rw uart 7 driver. the default value may be changed by auto-loading from eeprom. 0000b: rs232 0001b: rs422 1011b: rs485-4w 1111b: rs485-2w reset to 0000b. 6.2.40. power management control parameter ? offset b8h bit function type description 5:0 power management control parameter rw the default value may be changed by auto-loading from eeprom. reset to 000001b. 31:6 reserved ro reset to 0000000h. 6.2.41. debug register 1 ? offset bch (test purpose only) bit function type description 31:0 debug register 1 ro used for test purpose only. reset to 00000000h. 6.2.42. debug register 2 ? offset c0h (test purpose only) bit function type description 31:0 debug register 2 ro used for test purpose only. reset to 00000000h. 6.2.43. debug register 3 ? offset c4h (test purpose only) bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 34 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 31:0 debug register 3 ro used for test purpose only. reset to 00000000h. 6.2.44. debug register 4 ? offset c8h (test purpose only) bit function type description 0 low driver current hwint it indicates the status of the strapping pin lodrv. the default value may be changed by auto-loading from eeprom. 1 high driver current hwint it indicates the status of the strapping pin hidrv. the default value may be changed by auto-loading from eeprom. 5:2 driver transmit current hwint it indicates the status of the strapping pins dtx[3:0]. the default value may be changed by auto-loading from eeprom. 9:6 de-emphasis transmit equalization hwint it indicates the status of the strapping pins deq[3:0]. the default value may be changed by auto-loading from eeprom. 11:10 receive termination adjustment hwint it indicates the status of the strapping pins rxtrmadj[1:0]. the default value may be changed by auto-loading from eeprom. 13:12 transmit termination adjustment hwint it indicates the status of the strapping pins txtrmadj[1:0]. the default value may be changed by auto-loading from eeprom. 31:14 reserved ro reset to 00000h. 6.2.45. gpio control register ? offset d8h bit function type description 7:0 gpio input ro the current state of the gpio[x] pin can be read from bit[x] in this register, where x=7 to 0. the bits are effective only when the corresponding gpio i/o enable bits are set to ?0?. 15:8 gpio i/o enable rw these 8 bits determine whether the gpio pins are input or output pins. bit[x+8] corresponds to gpio[x], where x=7 to 0. if the bit is set to ?0?, the corresponding gpio pin is an input pin. if the bit is set to ?1?, the corresponding gpio pin is an output pin. 23:16 gpio output rw the current state of the gpio[x] pin can be written by bit[x+16] in this register, where x=7 to 0. the bits are effective only when the corresponding gpio i/o enable bits are set to ?1?. 31:24 reserved ro reserved 6.2.46. eeprom control register ? offset dch bit function type description 0 eeprom start rw starts the eeprom read or write cycle. reset to 0b. 1 reserved ro reset to 0b. 2 eeprom preload control rw enable preload start. reset to 0b. 4:3 eeprom operation command rw eeprom operation command. 00b: reserved 01b: write operation command 10b: read operation command 11b: reserved reset to 00b. 15:5 eeprom address rw eeprom rw address. reset to 000h. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 35 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 31:16 eeprom write data buffer rw eeprom write data buffer register. reset to 0000h. 6.2.47. pci express capability id register ? offset e0h bit function type description 7:0 enhanced capabilities id ro read as 10h to indicate that these are pci express enhanced capability registers. 6.2.48. next item pointer register ? offset e0h bit function type description 15:8 next item pointer ro read as 00h. no other ecp registers. reset to 00h. 6.2.49. pci express capabilities register ? offset e0h bit function type description 19:16 capability version ro read as 0001b to indicate the i/o bridge is compliant to revision 1.0a of pci express base specifications. 23:20 device/port type ro indicates the type of legacy pci express endpoint device. reset to 1h. 24 slot implemented ro it is not implemented. hardwired to 0b. 29:25 interrupt message number ro it is not implemented. hardwired to 00000b. 31:30 reserved ro reset to 00b. 6.2.50. device capabilities register ? offset e4h bit function type description 2:0 max_payload_size supported ro indicates the maximum payload size that the i/o bridge can support for tlps. the i/o bridge supports 128 bytes max payload size. reset to000b. 4:3 phantom functions supported ro it is not implemented. hardwired to 00b. 5 extended tag field supported ro it is not implemented. hardwired to 0b. 8:6 endpoint l0s acceptable latency ro acceptable total latency that an endpoint can withstand due to the transition from l0s state to the l0 state. reset to 000b. 11:9 endpoint l1 acceptable latency ro acceptable total latency that an endpoint can withstand due to the transition from l1 state to the l0 state. reset to 000b. 12 attention button present ro it is not implemented. hardwired to 0b. 13 attention indicator present ro it is not implemented. hardwired to 0b. 14 power indicator present ro it is not implemented. hardwired to 0b. 15 role_base error reporting ro when set, indicated that the de vice implements the functionality originally defined in the error reporting ecn. the default value may be changed by auto-loading from eeprom. reset to 1b. 17:16 reserved ro reset to 00b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 36 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 25:18 captured slot power limit value ro in combination with the slot power limit scale value, specifies the upper limit on power supplied by slot. this value is set by the set_slot_power_limit message or hardwired to ?00h?. reset to 00b. 27:26 captured slot power limit scale ro specifies the scale used for the slot power limit value. this value is set by the set_slot_power_limit message or hardwired to ?00b?. reset to 00b. 31:28 reserved ro reset to 0h. 6.2.51. device control register ? offset e8h bit function type description 0 correctable error reporting enable rw 0b: disable correctable error reporting. 1b: enable correctable error reporting. reset to 0b. 1 non-fatal error reporting enable rw 0b: disable non-fatal error reporting. 1b: enable non-fata l error reporting. reset to 0b. 2 fatal error reporting enable rw 0b: disable fatal error reporting. 1b: enable fatal error reporting. reset to 0b. 3 unsupported request reporting enable rw 0b: disable unsupported request reporting. 1b: enable unsupporte d request reporting. reset to 0b. 4 enable relaxed ordering ro it is not implemented. reset to 0b. 7:5 max_payload_size rw this field sets maximum tlp payload size for the device. permissible values that can be programmed are indicated by the max_payload_size supported in the device capabilities register. any value exceeding the max_pa yload_size supported written to this register results into cl amping to the max_payload_size supported value. reset to 000b. 8 extended tag field enable ro it is not implemented. hardwired to 0b. 9 phantom function enable ro it is not implemented. hardwired to 0b. 10 auxiliary (aux) power pm enable rws when set, indicates that the i/o bridge is enabled to draw aux power independent of pme aux power. reset to 0b. 11 enable no snoop ro it is not implemented. hardwired to 0b. 14:12 max_read_ request_size ro it is not implemented. hardwired to 000b. 15 reserved ro reset to 0b. 6.2.52. device status register ? offset e8h bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 37 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 16 correctable error detected rw1c asserted when correctable error is detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. reset to 0b. 17 non-fatal error detected rw1c asserted when non-fatal error is de tected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. reset to 0b. 18 fatal error detected rw1c asserted when fatal error is dete cted. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. reset to 0b. 19 unsupported request detected rw1c asserted when unsupported request is detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. reset to 0b. 20 aux power detected ro asserted when the aux power is detected by the i/o bridge reset to 1b. 21 transactions pending ro it is not implemented. hardwired to 0b. 31:22 reserved ro reset to 000h. 6.2.53. link capabilities register ? offset ech bit function type description 3:0 maximum link speed ro indicates the maximum link speed of the given pcie link. defined encodings are: 0001b, which indicates 2.5 gb/s link reset to 1h. 9:4 maximum link width ro indicates the maximum width of the given pcie link. reset to 000001b (x1). 11:10 active state power management (aspm) support ro indicates the level of aspm supported on the given pcie link. the i/o bridge supports l0s and l1 entry. the default value may be changed by auto-loading from eeprom. reset to 11b. 14:12 l0s exit latency ro indicates the l0s exit latency for th e given pcie link. the length of time this i/o bridge requires to complete transition from l0s to l0 is in the range of 256ns to less th an 512ns. the default value may be changed by auto-loading from eeprom. reset to 011b. 17:15 l1 exit latency ro indicates the l1 exit latency for the given pcie link. the length of time this i/o bridge requires to co mplete transition from l1 to l0 is in the range of 16us to less th an 32us. the default value may be changed by auto-loading from eeprom. reset to 000b. 23:18 reserved ro reset to 00000b. 31:24 port number ro it is not implemented. hardwired to 00h. 6.2.54. link control register ? offset f0h bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 38 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 1:0 active state power management (aspm) control rw 00b: aspm is disabled. 01b: l0s entry enabled. 10b: l1 entry enabled. 11b: l0s and l1 entry enabled. note that the receiver must be capable of entering l0s even when the field is disabled. reset to 00b. 2 reserved ro reset to 0h. 3 read completion boundary (rcb) ro it is not implemented. hardwired to 0b. 4 link disable ro it is not implemented. hardwired to 0b. 5 retrain link ro it is not implemented. hardwired to 0b. 6 common clock configuration rw 0b: the components at both ends of a link are operating with asynchronous reference clock. 1b: the components at both ends of a link are operating with a distributed common reference clock. reset to 0b. 7 extended synch rw when set, it transmits 4096 fts ordered sets in the l0s state for entering l0 state and transmits 1024 ts1 ordered sets in the l1 state for entering l0 state reset to 0b. 15:8 rsvdp ro reset to 00h. 6.2.55. link status register ? offset f0h bit function type description 19:16 link speed ro indicates the negotiated link speed of the given pcie link. defined encodings are: 0001b, which indicates 2.5 gb/s link reset to 1h. 25:20 negotiated link width ro indicates the negotiated width of the given pcie link, reset to 000001b. 26 training error ro when set, indicates a link training error occurred. this bit is cleared by hardware upon successful training of the link to the l0 link state. reset to 0b. 27 link training ro when set, indicates the link training is in progress. hardware clears this bit once link training is complete. reset to 0b. 28 slot clock configuration ro it is not implemented. hardwired to 0b. 31:29 reserved ro reset to 000b. 6.2.56. pci express advanced error reporting capability id register ? offset 100h bit function type description 15:0 extended capabilities id ro read as 0001h to indicate that these are pci express extended capability registers for ad vance error reporting. 6.2.57. capability version ? offset 100h bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 39 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 19:16 capability version ro indicates pci-sig defined pci expr ess capability structure version number. reset to 1h. 6.2.58. next item pointer register ? offset 100h bit function type description 31:20 next capability offset ro read as 00h. no other ecp registers. reset to 000h. 6.2.59. uncorrectable error status register ? offset 104h bit function type description 0 training error status rw1cs when set, indicates that the training error event has occurred. reset to 0b. 3:1 reserved ro reset to 000b. 4 data link protocol error status rw1cs when set, indicates that the data link protocol error event has occurred. reset to 0b. 11:5 reserved ro reset to 0000000b. 12 poisoned tlp status rw1cs when set, indicates that a pois oned tlp has been received or generated. reset to 0b. 13 flow control protocol error status rw1cs when set, indicates that the flow control protocol error event has occurred. reset to 0b. 14 completion timeout status rw1cs when set, indicates that the completion timeout event has occurred. reset to 0b. 15 completer abort status rw1cs when set, indicates that the completer abort event has occurred. reset to 0b. 16 unexpected completion status rw1cs when set, indicates that the unexpected completion event has occurred. reset to 0b. 17 receiver overflow status rw1cs when set, indicates that the receiver overflow event has occurred. reset to 0b. 18 malformed tlp status rw1cs when set, indicates that a malf ormed tlp has been received. reset to 0b. 19 ecrc error status rw1cs when set, indicates that an e crc error has been detected. reset to 0b. 20 unsupported request error status rw1cs when set, indicates that an unsupported request event has occurred. reset to 0b. 31:21 reserved ro reset to 000h. 6.2.60. uncorrectable error mask register ? offset 108h bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 40 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 0 training error mask rws when set, the training error event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 3:1 reserved ro reset to 000b. 4 data link protocol error mask rws when set, the data link protocol error event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 11:5 reserved ro reset to 0000000b. 12 poisoned tlp mask rws when set, an event of poisoned tlp has been received or generated is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 13 flow control protocol error mask rws when set, the flow control protocol error event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 14 completion timeout mask rws when set, the completion timeout ev ent is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 15 completer abort mask rws when set, the completer abort event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 16 unexpected completion mask rws when set, the unexpected comple tion event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 17 receiver overflow mask rws when set, the receiver overflow ev ent is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 18 malformed tlp mask rws when set, an event of malformed tlp has been received is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 19 ecrc error mask rws when set, an event of ecrc error has been detected is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 20 unsupported request error mask rws when set, the unsupported request event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 31:21 reserved ro reset to 000h. 6.2.61. uncorrectable error severity register ? offset 10ch bit function type description 0 training error severity rws 0b: non-fatal. 1b: fatal. reset to 1b. 3:1 reserved ro reset to 000b. 4 data link protocol error severity rws 0b: non-fatal. 1b: fatal. reset to 1b. 11:5 reserved ro reset to 0000000b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 41 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 12 poisoned tlp severity rws 0b: non-fatal. 1b: fatal. reset to 0b. 13 flow control protocol error severity rws 0b: non-fatal. 1b: fatal. reset to 1b. 14 completion timeout error severity rws 0b: non-fatal. 1b: fatal. reset to 0b. 15 completer abort severity rws 0b: non-fatal. 1b: fatal. reset to 0b. 16 unexpected completion severity rws 0b: non-fatal. 1b: fatal. reset to 0b. 17 receiver overflow severity rws 0b: non-fatal. 1b: fatal. reset to 1b. 18 malformed tlp severity rws 0b: non-fatal. 1b: fatal. reset to 1b. 19 ecrc error severity rws 0b: non-fatal. 1b: fatal. reset to 0b. 20 unsupported request error severity rws 0b: non-fatal. 1b: fatal. reset to 0b. 31:21 reserved ro reset to 000h . 6.2.62. correctable error status register ? offset 110h bit function type description 0 receiver error status rw1cs when set, the receiver error event is detected. reset to 0b. 5:1 reserved ro reset to 0h. 6 bad tlp status rw1cs when set, the event of bad tlp has been received is detected. reset to 0b. 7 bad dllp status rw1cs when set, the event of bad dllp has been received is detected. reset to 0b. 8 replay_num rollover status rw1cs when set, the replay_num rollover event is detected. reset to 0b. 11:9 reserved ro reset to 000b. 12 replay timer timeout status rw1cs when set, the replay timer timeout event is detected. reset to 0b. 31:13 reserved ro reset to 00000h. 6.2.63. correctable error mask register ? offset 114h bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 42 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 0 receiver error mask rws when set, the receiver error event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 5:1 reserved ro reset to 0h. 6 bad tlp mask rws when set, the event of bad tlp has been received is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 7 bad dllp mask rws when set, the event of bad dllp ha s been received is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 8 replay_num rollover mask rws when set, the replay_num rollov er event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 11:9 reserved ro reset to 000b. 12 replay timer timeout mask rws when set, the replay timer time out event is not logged in the header log register and not issued as an error message to rc either. reset to 0b. 31:13 reserved ro reset to 00000h . 6.2.64. advance error capabilities and control register ? offset 118h bit function type description 4:0 first error pointer ros it indicates the bit position of the first error reported in the uncorrectable error status register. reset to 00000b. 5 ecrc generation capable ro when set, it indicates the i/o bri dge has the capability to generate ecrc. reset to 1b. 6 ecrc generation enable rws when set, it enables the gene ration of ecrc when needed. reset to 0b. 7 ecrc check capable ro when set, it indicates the i/o br idge has the capability to check ecrc. reset to 1b. 8 ecrc check enable rws when set, the function of checking ecrc is enabled. reset to 0b. 31:9 reserved ro reset to 000000h. 6.2.65. header log register ? offset from 11ch to 128h bit function type description 3:0 1 st dword ro hold the 1st dword of tlp header. the head byte is in big endian. 7:4 2 nd dword ro hold the 2nd dword of tlp header. the head byte is in big endian. 11:8 3 rd dword ro hold the 3rd dword of tlp header. the head byte is in big endian. 15:12 4 th dword ro hold the 4th dword of tlp header. the head byte is in big endian. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 43 of 71 march 2011 ? revision 1.4 pericom semiconductor 11-0039
pi7c9x7958 pci express? octal uart datasheet page 44 of 71 march 2011 ? revision 1.4 pericom semiconductor 7. uart register description 7.1. registers in i/o mode each uart channel has a dedicated 8-byte register block in i/o mode. the register block can be accessed by the uart i/o base address, which is obtained by adding the uart register offset to the content of the base address register 0 (bar0). the following diagram shows the arrangement of individual uart register blocks. 000h uart0 registers 008h uart1 registers 010h uart2 registers 018h uart3 registers 020h uart4 registers 028h uart5 registers 030h uart6 registers 038h uart7 registers uart i/o base address (bar0 + uart register offset) uart register offset figure 7-1 uart register block arrangement in i/o mode table 7-1 uart base address in i/o mode uart uart i/o base address uart0 bar0 + 000h uart1 bar0 + 008h uart2 bar0 + 010h uart3 bar0 + 018h uart4 bar0 + 020h uart5 bar0 + 028h uart6 bar0 + 030h uart7 bar0 + 038h 11-0039
pi7c9x7958 pci express? octal uart datasheet page 45 of 71 march 2011 ? revision 1.4 pericom semiconductor each register in the uart register block can be access by adding an offset to the uart i/o base address. the following table lists the arrangement of the registers in the uart register block in i/o mode. table 7-2 registers in i/o mode offset register name mnemonic register type uart i/o base address + 00h receive holding register rhr ro uart i/o base address + 00h transmit holding register thr wo uart i/o base address + 01h interrupt enable register ier rw uart i/o base address + 02h interrupt status register isr ro uart i/o base address + 02h fifo control register fcr wo uart i/o base address + 03h line control register lcr rw uart i/o base address + 04h modem control register mcr rw uart i/o base address + 05h line status register lsr ro uart i/o base address + 06h modem status register msr ro uart i/o base address + 07h spec ial function register sfr rw additional standard registers (required lcr[7] = 1) uart i/o base address + 00h division latch low dll rw uart i/o base address + 01h division latch high dlh rw uart i/o base address + 02h sample clock register scr rw 7.1.1. receive holding register ? offset 00h bit function type description 7:0 rx holding ro data received reset to 00h. 7.1.2. transmit holding register ? offset 00h bit function type description 7:0 tx holding wo data to transmit reset to 00h. 7.1.3. interrupt enable register ? offset 01h bit function type description 0 rx data available interrupt rw 0b: disable the receive data ready interrupt 1b: enable the receiv e data ready interrupt reset to 0b. 1 tx empty interrupt rw 0b: disable the transmit holding register empty interrupt 1b: enable the transmit holding register empty interrupt reset to 0b. 2 rx status interrupt rw 0b: disable the receive line status interrupt 1b: enable the receive line status interrupt reset to 0b. 3 modem status interrupt rw 0b: disable the modem status register interrupt 1b: enable the modem status register interrupt reset to 0b. 4 xoff/special character interrupt rw 0b: disable the software flow control interrupt 1b: enable the software flow control interrupt reset to 0b. 5 rts interrupt rw 0b: disable rts/dtr interrupt 1b: enable rts/dtr interrupt reset to 0b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 46 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 6 cts interrupt rw 0b: disable cts/dsr interrupt 1b: enable cts/dsr interrupt reset to 0b. 7 reserved rw 7.1.4. interrupt status register ? offset 02h bit function type description 7:0 interrupt status ro 0b: an interrupt is pending 1b: no interrupt pending reset to c1h. interrupt status bits priority level bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 interrupt source 1 1 1 0 0 0 1 1 0 rx data error 2 1 1 0 0 0 1 0 0 rx data available 3 1 1 0 0 1 1 0 0 rx time-out 4 1 1 0 0 0 0 1 0 tx fifo empty 5 1 1 0 0 0 0 0 0 modem status change 6 1 1 0 1 0 0 0 0 xoff or special character detected 7 1 1 1 0 0 0 0 0 cts or rts state changed x 1 1 0 0 0 0 0 1 no interrupt pending 7.1.5. fifo control register ? offset 02h bit function type description 0 fifo mode enable wo 0b : disable the fifo mode 1b: enable the fifo mode reset to 0b. 1 rx fifo flush wo 0b: no action 1b: reset the receive fifo, self -clear after resetting the fifo reset to 0b. 2 tx fifo flush wo 0b: no action 1b: reset the transmit fifo, self-clear after resetting the fifo reset to 0b. 3 reserved wo reset to 0b. 5:4 tx trigger level wo in the enhanced mode. 00b: 16 01b: 32 10b: 64 11b: 112 reset to 00b. in the non-enhanced mode 00b: 1 01b: 4 10b: 8 11b: 14 in the enhanced mode 00b: 15 01b: 31 10b: 63 11b: 111 7:6 rx trigger level wo reset to 00b. 7.1.6. line control register ? offset 03h bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 47 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 1:0 data length rw 00b: 5-bit data length 01b: 6-bit data length 10b: 7-bit data length 11b: 8-bit data length reset to 11b. 2 stop-bit length rw bit 2 value data length stop bit length 0 5,6,7,8 1 1 5 1.5 1 6,7,8 2 reset to 0b. 5:3 parity type rw bit 5 bit 4 bit 3 parity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 mark 1 1 1 space reset to 000b. 6 transmission break rw 0b: no transmit break condition 1b: force the transmitter output to a space for alerting the remote receiver of a line break condition. reset to 0b. 7 divisor latch enable rw 0b: data registers are selected 1b: divisor latch registers are selected reset to 0b. 7.1.7. modem control register ? offset 04h bit function type description 0 dtr pin control rw 0b: forces dtr output high 1b: forces dtr output low reset to 0b. 1 rts pin control rw 0b: forces rts output high 1b: forces rts output low reset to 0b. 2 output 1 rw when the internal loopba ck mode is enabled by setting modem control register bit[4], output of the output1 is routed to ri. reset to 0b. 3 output 2 rw when the internal loopba ck mode is enabled by setting modem control register bit[4], output of the output2 is routed to dcd. reset to 0b. 4 internal loopback mode rw 0b: disables internal loopback mode 1b: enables internal loopback mode reset to 0b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 48 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 5 afe rw autoflow control enable. wh en the afe is enabled, autoflow control is enabled. when it is di sabled, the diagnostic mode is enabled. in the diagnostic mode, transmitted data is immediately received. when afe is set to ?1?, mcr bit 1 is used to enable and disable the auto-rts. mcr bit 5 (afe) mcr bit 1 (rts) configuration 1 1 auto-rts and auto-cts are enabled (autoflow control enabled). 1 0 only auto-cts is enabled. 0 x auto-rts and auto-cts are disabled. reset to 0b. 6 reserved reset to 0b. 7 enhanced transmission rw 0b: insert 1, 1.5 or 2 stop-bits between two transmitted characters. 1b: insert 0.5 stop-bits between two transmitted characters. note: enabling feature may result in certain compatibility issues. this feature is only recommended when using two pericom uart devices. reset to 0b. 7.1.8. line status register ? offset 05h bit function type description 0 rx data available ro 0b: no data in the receive fifo 1b: data in the receive fifo reset to 0b. 1 rx fifo overrun ro 0b: no overrun error 1b: overrun error reset to 0b. 2 rx parity error ro 0b: no parity error 1b: parity error reset to 0b. 3 rx frame error ro 0b: no framing error 1b: framing error reset to 0b. 4 rx break error ro 0b: no break condition 1b: break condition reset to 0b. 5 tx empty ro 0b: tx holding register is not empty. 1b: tx holding register is empty. reset to 0b. 6 tx complete ro 0b: tx shift register is not empty. 1b: tx shift register is empty. reset to 0b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 49 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 7 rx data error ro 0b: no rx fifo error 1b: rx fifo error reset to 0b. 7.1.9. modem status register ? offset 06h bit function type description 0 delta cts ro 0b: no change in cts input. 1b: indicates the cts i nput has changed state. this bit is read-clear. reset to 0b. 1 delta dsr ro 0b: no change in dsr input. 1b: indicates the dsr input has changed state. this bit is read-clear. reset to 0b. 2 trailing ri edge ro 0b: no change in ri input 1b: indicates the ri input has changed state from the logic 0 to the logic 1. this bit is read-clear. reset to 0b. 3 delta dcd ro 0b: no change in dcd input 1b: indicates the dcd input has changed state. this bit is read-clear. reset to 0b. 4 cts ro 0b: the cts input state is the logic 0 1b: the cts input state is the logic 1 reset to 0b. 5 dsr ro 0b: the dsr input state is the logic 0 1b: the dsr input state is the logic 1 reset to 0b. 6 ri ro the input state of ri pin reset to 0b. 7 dcd ro the input state of dcd pin reset to 0b. 7.1.10. special function register ? offset 07h bit function type description 0 force transmission rw forces tran smitter to always to transmit data. 1b: enabled 0b: disabled reset to 0b. 1 auto dsr and dtr flow control rw auto dsr and dtr flow control enable 1b: enables dsr and dtr auto flow control 0b: disables dsr and dtr auto flow control reset to 0b. 2 reserved ro reset to 0b. 3 reserved ro reset to 0b. 4 reserved rw reset to 0b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 50 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 5 950 mode rw 1b: enables 950 mode 0b: non-950 mode reset to 0b. 6 rfd / lsr counter select rw 1b: offset 15 bit[7:0] acts as the line status register counter 0b: offset 15 bit[7:0] acts as the receive fifo data counter reset to 0b. 7 tfd / scr select rw 1b: offset 16 bit[7:0] acts as the transmit fifo data counter 0b: offset 16 bit[7:0] acts as the sample clock register reset to 0b. 7:6 reserved rw reset to 00b. 7.1.11. divisor latch low register ? offset 00h, lcr[7] = 1 bit function type description 7:0 divisor low rw lower-part of the divisor register reset to 00h. 7.1.12. divisor latch high register ? offset 01h, lcr[7] = 1 bit function type description 7:0 divisor high rw higher-part of the divisor register reset to 00h. 7.1.13. sample clock register ? offset 02h, lcr[7] = 1 bit function type description 3:0 sample clock rw this register determines the sa mple clock value (sc) used in the baud rate generator. please refer to 5.2.12 baud rate generation for more detail 0000b: sc = 16 0001b: sc = 15 0010b: sc = 14 0011b: sc = 13 0100b: sc = 12 0101b: sc = 11 0110b: sc = 10 0111b: sc = 9 1000b: sc = 8 1001b: sc = 7 1010b: sc = 6 1011b: sc = 5 1100b: sc = 4 other settings are reserved. reset to 0h. 7:4 reserve r reset to 0h. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 51 of 71 march 2011 ? revision 1.4 pericom semiconductor 7.2. registers in memory-mapping mode each uart channel has a dedicated 512-byte register block in memory mode. the register block can be accessed by the uart memory base address, which is obtained by adding the uart register offset to the content of the base address register 1 (bar1). the following diagram shows the arrangement of individual uart register blocks. 0000h uart0 registers 0200h uart1 registers 0400h uart2 registers 0600h uart3 registers 0800h uart4 registers 0a00h uart5 registers 0c00h uart6 registers 0e00h uart7 registers uart memory base address (bar1 + uart register offset) uart register offset figure 7-2 uart register block arrangement in memory mode table 7-3 uart base address in memory mode uart uart i/o base address uart0 bar1 + 0000h uart1 bar1 + 0200h uart2 bar1 + 0400h uart3 bar1 + 0600h uart4 bar1 + 0800h uart5 bar1 + 0a00h uart6 bar1 + 0c00h uart7 bar1 + 0e00h 11-0039
pi7c9x7958 pci express? octal uart datasheet page 52 of 71 march 2011 ? revision 1.4 pericom semiconductor each register in the uart register block can be access by adding an offset to the uart memory base address. the following table lists the arrangement of the registers in the uart register block in memory mode. table 7-4 memory-map mode offset register name mnemonic register type uart memory base address + 00h receive holding register rhr ro uart memory base address + 00h transmit holding register thr wo uart memory base address + 01h interrupt enable register ier rw uart memory base address + 02h interrupt status register isr ro uart memory base address + 02h fifo control register fcr wo uart memory base address + 04h line control register lcr rw uart memory base address + 04h modem control register mcr rw uart memory base address + 05h line status register lsr ro uart memory base address + 06h modem status register msr ro uart memory base address + 07h special function register sfr rw uart memory base address + 08h divisor latch low dll wo uart memory base address + 09h divisor latch high dlh wo uart memory base address + 0ah enhanced function register efr rw uart memory base address + 0bh xon 1 character/special character 1 xon1 rw uart memory base address + 0ch xon 2 character/special character 2 xon2 rw uart memory base address + 0dh xoff 1 character/special character 3 xoff1 rw uart memory base address + 0eh xoff 2 character/special character 3 xoff2 rw uart memory base address + 0fh advanced status register asr rw uart memory base address + 10h transmitter interrupt trigger level ttl rw uart memory base address + 11h receiver interrupt trigger level rtl rw uart memory base address + 12h automatic flow control lower trigger level fcl rw uart memory base address + 13h automatic flow control lower higher level fch rw uart memory base address + 14h baud rate prescale cpr rw uart memory base address + 15h receive fifo data counter / line status register counter rfd / lsr counter ro uart memory base address + 16h transmit fifo data counter / sample clock register tfd counter / scr rw uart memory base address + 17h global register of lsr glsr rw uart memory base address + 100h ~17fh uart0 fifo data register. use this register to map fifo data content. fifo_d rw uart memory base address + 180h ~1ffh uart0 fifo data lsr register. use this register to map fifo data relative lsr content. fifo_lsr rw 7.2.1. receive holding register ? offset 00h bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 53 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 7:0 rx holding ro when data are read fr om the receive holding register (rhr), they are removed from the top of the receiver?s associated fifos, which holds a queue of da ta received by the receiver. data read from the rhr when the fifos are empty are invalid. the line status register (lsr) indicates the full or empty status of the fifos. reset to 00h. 7.2.2. transmit holding register ? offset 00h bit function type description 7:0 tx holding wo when data are written to the transmit holding register (thr), they are written to the bottom of the transmitter?s associated fifos, which holds a queue of data to be transmitted by the transmitter. data written to the thr when the fifos are full are lost. the line status register (lsr) indicates the full or empty status of the fifos. reset to 00h. 7.2.3. interrupt enable register ? offset 01h bit function type description 0 rx data available interrupt rw 0b: disable the receive data ready interrupt 1b: enable the receiv e data ready interrupt reset to 0b. 1 tx empty interrupt rw 0b: disable the transmit holding register empty interrupt 1b: enable the transmit holding register empty interrupt reset to 0b. 2 rx error status rw 0b: disable the receive line status interrupt 1b: enable the receive line status interrupt reset to 0b. 3 modem status interrupt rw 0b: disable the modem status register interrupt 1b: enable the modem status register interrupt reset to 0b. 4 xoff/special character interrupt rw 0b: disable the software flow control interrupt 1b: enable the software flow control interrupt reset to 0b. 5 rts interrupt rw 0b: disable rts/dtr interrupt 1b: enable rts/dtr interrupt reset to 0b. 6 cts interrupt rw 0b: disable cts/dsr interrupt 1b: enable cts/dsr interrupt reset to 0b. 7 reserved rw reset to 0b. 7.2.4. interrupt status register ? offset 02h bit function type description 11-0039
pi7c9x7958 pci express? octal uart datasheet page 54 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 7:0 interrupt status ro 0b: an interrupt is pending 1b: no interrupt pending reset to c1h. interrupt status bits priority level bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 interrupt source 1 1 1 0 0 0 1 1 0 rx data error 2 1 1 0 0 0 1 0 0 rx data available 3 1 1 0 0 1 1 0 0 rx time-out 4 1 1 0 0 0 0 1 0 tx fifo empty 5 1 1 0 0 0 0 0 0 modem status change 6 1 1 0 1 0 0 0 0 xoff or special character detected 7 1 1 1 0 0 0 0 0 cts or rts state changed x 1 1 0 0 0 0 0 1 no interrupt pending 7.2.5. fifo control register ? offset 02h bit function type description 0 fifo mode enable wo 0b : disable the fifo mode 1b: enable the fifo mode reset to 0b. 1 rx fifo flush wo 0b: no action 1b: reset the receive fifo, self -clear after resetting the fifo reset to 0b. 2 tx fifo flush wo 0b: no action 1b: reset the transmit fifo, self-clear after resetting the fifo reset to 0b. 3 reserved wo reset to 0b 5:4 tx trigger level wo in the enhanced mode: 00b: 16 01b: 32 10b: 64 11b: 112 reset to 00b. in the non-enhanced mode 00b: 1 01b: 4 10b: 8 11b: 14 in the enhanced mode 00b: 15 01b: 31 10b: 63 11b: 111 7:6 rx trigger level wo reset to 00b. 7.2.6. line control register ? offset 03h bit function type description 1:0 data length rw 00b: 5-bit data length 01b: 6-bit data length 10b: 7-bit data length 11b: 8-bit data length reset to 00b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 55 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 2 stop-bit length rw bit 2 value data length stop bit length 0 5,6,7,8 1 1 5 1.5 1 6,7,8 2 reset to 0b. 5:3 parity type rw bit 5 bit 4 bit 3 parity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 mark 1 1 1 space reset to 000b. 6 transmission break rw 0b: no transmit break condition 1b: force the transmitter output to a space for alerting the remote receiver of a line break condition. reset to 0b. 7 divisor latch enable rw 0b: data registers are selected 1b: divisor latch registers are selected reset to 0b. 7.2.7. modem control register ? offset 04h bit function type description 0 dtr pin control rw 0b: forces dtr output high 1b: forces dtr output low reset to 0b. 1 rts pin control rw 0b: forces rts output high 1b: forces rts output low reset to 0b. 2 output 1 rw when the internal loopba ck mode is enabled by setting modem control register bit[4], output of the output1 is routed to ri. reset to 0b. 3 output 2 rw when the internal loopba ck mode is enabled by setting modem control register bit[4], output of the output2 is routed to dcd. reset to 0b. 4 internal loopback mode rw 0b: disables internal loopback mode 1b: enables internal loopback mode reset to 0b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 56 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 5 afe rw autoflow control enable. wh en the afe is enabled, autoflow control is enabled. when it is di sabled, the diagnostic mode is enabled. in the diagnostic mode, transmitted data is immediately received. when afe is set to ?1?, mcr bit 1 is used to enable and disable the auto-rts. mcr bit 5 (afe) mcr bit 1 (rts) configuration 1 1 auto-rts and auto-cts are enabled (autoflow control enabled). 1 0 only auto-cts is enabled. 0 x auto-rts and auto-cts are disabled. reset to 0b. 6 reserved reset to 0b. 7 enhanced transmission rw 0b: insert 1, 1.5 or 2 stop-bits between two transmitted characters. 1b: insert 0.5 stop-bits between two transmitted characters. note: enabling feature may result in certain compatibility issues. this feature is only recommended when using two pericom uart devices. reset to 0b. 7.2.8. line status register ? offset 05h bit function type description 0 rx data available ro 0b: no data in the receive fifo 1b: data in the receive fifo reset to 0b. 1 rx fifo overrun ro 0b: no overrun error 1b: overrun error reset to 0b. 2 rx parity error ro 0b: no parity error 1b: parity error reset to 0b. 3 rx frame error ro 0b: no framing error 1b: framing error reset to 0b. 4 rx break error ro 0b: no break condition 1b: break condition reset to 0b. 5 tx empty ro 0b: tx holding register is not empty. 1b: tx holding register is empty. reset to 0b. 6 tx complete ro 0b: tx shift register is not empty. 1b: tx shift register is empty. reset to 0b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 57 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 7 rx data error ro 0b: no rx fifo error 1b: rx fifo error reset to 0b. 7.2.9. modem status register ? offset 06h bit function type description 0 delta cts ro 0b: no change in cts input. 1b: indicates the cts i nput has changed state. this bit is read-clear. reset to 0b. 1 delta dsr ro 0b: no change in dsr input. 1b: indicates the dsr input has changed state. this bit is read-clear. reset to 0b. 2 delta ri ro 0b: no change in ri input 1b: indicates the ri input has changed state from the logic 0 to the logic 1. this bit is read-clear. reset to 0b. 3 delta dcd ro 0b: no change in dcd input 1b: indicates the dcd input has changed state. this bit is read-clear. reset to 0b. 4 cts ro 0b: the cts input state is the logic 0 1b: the cts input state is the logic 1 reset to 0b. 5 dsr ro 0b: the dsr input state is the logic 0 1b: the dsr input state is the logic 1 reset to 0b. 6 ri ro the input state of ri pin reset to 0b. 7 dcd ro the input state of dcd pin reset to 0b. 7.2.10. special function register ? offset 07h bit function type description 0 force transmission rw forces tran smitter to always to transmit data. 1b: enabled 0b: disabled reset to 0b. 1 auto dsr and dtr flow control rw auto dsr and dtr flow control enable 1b: enables dsr and dtr auto flow control 0b: disables dsr and dtr auto flow control reset to 0b. 2 reserved ro reset to 0b. 3 reserved ro reset to 0b. 4 reserved rw reset to 0b. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 58 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 5 950 mode rw 1b: enables 950 mode 0b: non-950 mode reset to 0b. 6 rfd / lsr counter select rw 1b: offset 15 bit[7:0] acts as the line status register counter 0b: offset 15 bit[7:0] acts as the receive fifo data counter reset to 0b. 7 tfd / scr select rw 1b: offset 16 bit[7:0] acts as the transmit fifo data counter 0b: offset 16 bit[7:0] acts as the sample clock register reset to 0b. 7.2.11. divisor latch low register ? offset 08h bit function type description 7:0 divisor low rw lower-part of the divisor register reset to 00h. 7.2.12. divisor latch high register ? offset 09h bit function type description 7:0 divisor high rw higher-part of the divisor register reset to 00h. 7.2.13. enhanced function register ? offset 0ah bit function type description 1:0 in-band receive flow control mode rw when in-band receive flow control is enabled, the uart compares the received data with the programmed xoff character(s). when this occurs, the uart will disable transmission as soon as any current character transmission is complete. the uart then compares the received data with the programmed xon character(s). when a match occurs, the uart will re-enable transmission (see section 7.11.6). 00b: in-band receive flow control is disabled. 01b: single character in-band receive flow control enabled, recognising xon2 as the xon character and xoff2 as the xoff character. 10b: single character in-band receive flow control enabled, recognising xon1 as the xon character and xoff1 and the xoff character. 11b: the behavior of the receive flow control is dependent on the configuration of efr[3:2]. single character in-band receive flow control is enabled, accepting xon1 or xon2 as valid xon characters and xoff1 or xoff2 as valid xoff characters when efr[3:2] = ?01? or ?10?. efr[1:0] should not be set to ?11? when efr[3:2] is ?00?. reset to 00b. 3:2 in-band transmit flow control mode rw when in-band transmit flow control is enabled, xon/xoff character are inserted into th e data stream whenever the rfl passes the upper trigger le vel and falls below the lower trigger level respectively. for auto matic in-band flow control, bit 4 of efr must be set. the combinations of software transmit flow control can then be selected by programming efr[3:2] as follows. 00b: ? in-band transmit flow control is disabled logic. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 59 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 01b: ? single character in-band transmit flow control enabled, using xon2 as the xon ch aracter and xoff2 as the xoff character. 10b: ? single character in-band transmit flow control enabled, using xon1 as the xon ch aracter and xoff1 as the xoff character. 11b: the value efr[3:2] = ?11? is reserved for future use and should not be used reset to 00b. 4 enhanced mode rw 0b: ? non-enhanced mode. 1b: ? enhanced mode. enables the enhanced mode functions. if use addition function except 16550 mode. reset to 0b. 5 special character detection enable rw 0b: special character detection is disabled. 1b: while in enhanced mode (efr[4]=1), the uart compares the incoming receiver data w ith the xoff1 or xoff2 value and interrupt w ill be asserted. if in-band flow control is enabled, this bit must be set to ?1?. reset to 0b. 6 automatic rts flow control enable rw 0b: rts flow control is disabled. 1b: rts flow control is enabled in enhanced mode (i.e. efr[4] = 1), where the rts# pin will be forced inactive high if the rfl reaches the upper flow control threshold. this will be released when the rfl drops be low the lower threshold. 650 and 950-mode drivers should use different threshold level. reset to 0b. 7 automatic cts flow control enable rw 0b: cts flow control is disabled (default). 1b: cts flow control is enabled in enhanced mode (i.e. efr[4] = 1), where the data transmission is prevented whenever the cts# pin is held inactive high. 650 and 950-mode drivers should use different threshold level. reset to 0b. 7.2.14. xon special character 1 ? offset 0bh bit function type description 7:0 xon1 rw xon character 1. reset to 00h. 7.2.15. xon special character 2 ? offset 0ch bit function type description 7:0 xon2 rw xon character 2. reset to 00h. 7.2.16. xoff special character 1 ? offset 0dh bit function type description 7:0 xoff1 rw xoff character 1. reset to 00h. 7.2.17. xoff special character 2 ? offset 0eh 11-0039
pi7c9x7958 pci express? octal uart datasheet page 60 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 7:0 xoff2 rw xoff character 2. reset to 00h. 7.2.18. advance control register ? offset 0fh bit function type description 0 transmitter terminate condition ro indicates current transmitter te rminate condition. if transmitter is disabled by remote terminate, th e condition can be shown by this bit. 1b: disabled by remote terminate. 0b: the transmitter can transmit data normally. reset to 0b. 1 remote tx disable ro remote tx disable. 1b: if transmitter has sent xoff message or rts message, then dtr is inactive, and then it is enabled. 0b: otherwise reset to 0b. 2 xon/xoff detect ro when receiving a xon/xoff character from a remote transmitter, this bit is set to ?1?. otherwise, this bit is set to ?0?. the bit is read-clear. if the xoff/special character in terrupt is enabled, the xoff detect status is also reflected in the interrupt status register (priority level 6). 1b: event true 0b: event false reset to 0b. 3 special character detect ro when detecting the special char acters from a remote transmitter, this bit is set to ?1?. otherw ise, this bit is set to ?0?. the bit is read-clear. if the xoff/special character interr upt is enabled, the status is also reflected in the interrupt status register (priority level 6). 1b: event true 0b: event false reset to 0b. 7:4 reserved ro reset to 0000b. 7.2.19. transmit interrupt trigger level ? offset 10h bit function type description 7:0 ttl rw transmitter interrupt trigger level. reset to 00h. 7.2.20. receive interrupt trigger level ? offset 11h bit function type description 7:0 rtl rw receiver interrupt trigger level. reset to 00h. 7.2.21. flow control low trigger level ? offset 12h 11-0039
pi7c9x7958 pci express? octal uart datasheet page 61 of 71 march 2011 ? revision 1.4 pericom semiconductor bit function type description 7:0 fcl rw automatic flow c ontrol low trigger level. reset to 00h. 7.2.22. flow control high trigger level ? offset 13h bit function type description 7:0 fch rw automatic flow control high trigger level. reset to 00h. 7.2.23. clock prescale register ? offset 14h bit function type description 2:0 cprn rw n number in calculating the prescaler, which is used to generate the baud rate. reset to 000b. 7:3 cprm rw m number in calculating the prescaler, which is used to generate the baud rate. it is recommended that the value of the cprm be set to ?00001? or ?00010?. reset to 00001b. 7.2.24. receive fifo data counter ? offset 15h, sfr[6] = 0 the function of this register is selected by the special function register (offset 07h) bit 6. when sfr[6] is set to ?1?, this register functions as the receive fifo data counter. otherwise, it functions as the line status register counter. bit function type description 7:0 receive fifo data counter ro the receive fifo data counter indicates the amount of data in the receive fifo. reset to 00h. 7.2.25. line status register counter ? offset 15h, sfr[6] = 1 bit function type description 7:0 line status register counter ro the line status register counter indicates the amount of data in the lsr. reset to 00h. 7.2.26. transmit fifo data counter ? offset 16h, sfr[7] = 1 the function of this register is selected by the special function register (offset 07h) bit 7. when sfr[7] is set to ?1?, this register functions as the transmit fifo data counter. otherwise, it functions as the sample clock register. bit function type description 7:0 transmit fifo data counter ro the transmit fifo data counter indicates the amount of data in the transmit fifo. reset to 00h. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 62 of 71 march 2011 ? revision 1.4 pericom semiconductor 7.2.27. sample clock register ? offset 16h, sfr[7] = 0 bit function type description 3:0 sample clock rw this register determin es the sample clock value (sc) used in the baud rate generator. please refer to 5.2.12 baud rate generation for more detail 0000b: sc = 16 0001b: sc = 15 0010b: sc = 14 0011b: sc = 13 0100b: sc = 12 0101b: sc = 11 0110b: sc = 10 0111b: sc = 9 1000b: sc = 8 1001b: sc = 7 1010b: sc = 6 1011b: sc = 5 1100b: sc = 4 other settings are reserved. reset to 0h. 7:4 reserved ro reset to 0h. 7.2.28. global line status register ? offset 17h bit function type description 0 rx data available ro 0b: no data in the receive fifo 1b: data in the receive fifo reset to 0b. 1 rx fifo overrun ro 0b: no overrun error 1b: overrun error reset to 0b. 2 rx parity error ro 0b: no parity error 1b: parity error reset to 0b. 3 rx frame error ro 0b: no framing error 1b: framing error reset to 0b. 4 rx break error ro 0b: no break condition 1b: break condition reset to 0b. 5 tx empty ro 0b: tx holding register is not empty. 1b: tx holding register is empty. reset to 0b. 6 tx complete ro 0b: tx shift register is not empty. 1b: tx shift register is empty. reset to 0b. 7 rx data error ro 0b: no rx fifo error 1b: rx fifo error reset to 0b. 7.2.29. receive fifo data registers ? offset 100h ~ 17fh bit function type description 7:0 receive fifo data ro this register is used to map rx fifo data content. reset to 00h. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 63 of 71 march 2011 ? revision 1.4 pericom semiconductor 7.2.30. transmit fifo data registers ? offset 100h ~ 17fh bit function type description 7:0 transmit fifo data wo this register is used to map tx fifo to memory space. reset to 00h. 7.2.31. line status fifo registers ?offset 180h ~ 1ffh bit function type description 7:0 line status fifo ro this register is us ed to map fifo data relative lsr content. reset to 00h. 11-0039
pi7c9x7958 pci express? octal uart datasheet page 64 of 71 march 2011 ? revision 1.4 pericom semiconductor 8. eeprom interface the eeprom interface consists of five pins: sr_di (eeprom data input), sr_do (eeprom data output), sr_cs (eeprom chip select), sr_clk_o (eeprom clock output), and sr_org (eeprom organization). the device may control a 93c56 or compatible parts using 2k bits. the eeprom is used to initialize a number of registers before enumeration. this is accomplished at start-up when rts[0] is de-asserted, at which time the data from the eeprom is loaded. the eeprom interface is organized into a 16-bit base, and the device supplies a 7-bit eeprom word address. 8.1. auto mode eerpom access the device may access the eeprom in a word or byte format, which is decided by the sr_org# at start-up. if sr_org# is asserted at start-up, eeprom is accessed using the word format. otherwise, byte format is used. 8.2. eeprom mode at reset during a reset, the device will automatically load the information/data from the eeprom if the automatic load condition is met. the first offset in the eeprom contains a signature. if the signature is recognized, and if rts[0] is de-asserted, the autoload initiates right after the reset. 8.3. eeprom space address map and description eeprom address pcie register offset default value description 00h a868h check code 02h offset 00h bit[15:0] 12d8h ven dor id 04h offset 00h bit[31:16] 7958h device id 06h offset 2ch bit[15:0] 0000h subsytem vendor id 08h offset 2ch bit[31:16] 0000h subsytem id bit[0] - offset 80h bit[21] 0b device specific initialization: when set, the dsi is required. bit[3:1] - offset 80h bit[24:22] 111b aux. current: when set, the i/o bridge needs 375 ma in d3 state. bit[4] - offset 80h bit[25] 1b d1 support: when set, this bridge supports d1 power management state. bit[5] - offset 80h bit[26] 1b d2 support: when set, this bridge supports d2 power management state. bit[10:6] - offset 80h bit[31:27] 01000b pme support: when set, the pme supports d1 and d2 power management states. bit[11] - offset 84h bit[3] 1b no soft reset: when set, the device does not trigger the internal reset command during the transition from d3hot to d0 power state. 0ah bit[13:12] - offset a8h bit[14:13] 00b xpip csr0 0ch offset b0h bit[15:0] 0000h replay time-out counter 0eh offset b0h bit [31:16] 0000h acknowledge latency timer bit[1:0] - offset ech bit[11:10] 11b aspm capability support: when set, this bridge supports l0s and l1 entry bit[4:2] - offset ech bit[14:12] 011b exit l0s latency timer 10h bit[7:5] - offset ech bit[17:15] 000b exit l1 latency timer 12h offset b4h bit[15:0] 0000h uart transmitter drive enable: rs232/422/485-2w/485-4w selection for uart 0 to 3 11-0039
pi7c9x7958 pci express? octal uart datasheet page 65 of 71 march 2011 ? revision 1.4 pericom semiconductor eeprom address pcie register offset default value description 14h offset b4h bit[31:16] 0000h uart transmitter drive enable: rs232/422/485-2w/485-4w selection for uart 4 to 7 bit[1:0] - offset b8h bit[17:16] 01b pm control parameter: determines whether this bridge enters l1 or not when d3 condition occurs. bit[3:2] - offset b8h bit[19:18] 00b pm control parameter: determines the delay counter value when entering l1 16h bit[5:4] - offset b8h bit[21:20] 00b pm control parameter: determines whether this bridge asserts l0s/l1 handshake protocol 18h bit[13:0] - offset c8h bit[13:0] 0200h phy parameter bit[0] - offset c4h bit[15] 1b role based error report enable: indicates implement the role-base error reporting 1ah bit[15:8] - offset 34h bit[7:0] 80h capability list pointer: points to a linked list of new capabilities implemented by the device 1ch bit[7:0] - offset 08h bit[7:0] 00h revision id: indicates revision number of device 40h 12d8h check code 11-0039
pi7c9x7958 pci express? octal uart datasheet page 66 of 71 march 2011 ? revision 1.4 pericom semiconductor 9. electrical specification 9.1. absolute maximum ratings table 9-1 absolute maximum ratings (above which the useful life may be impa ired. for user guidelines, not tested.) storage temperature -65 o c to 150 o c ambient temperature with power applied -40 o c to 85 o c pci express supply voltage to ground potential (vdda, vddc, and vddcaux) -0.3v to 3.0v pci supply voltage to ground potential (vddr) -0.3v to 3.6v dc input voltage for pci express signals -0.3v to 3.0v dc input voltage for pci signals -0.5v to 5.75v note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specificati on is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 9.2. dc specifications table 9-2 dc electrical characteristics power pins min. typ. max. vdda 1.6v 1.8v 2.0v vddc 1.6v 1.8v 2.0v vddcaux 1.6v 1.8v 2.0v vtt vddc vddc 2.0v vddr 3.0v 3.3v 3.6v vdda: analog power supply for pci express interface vddc: digital power supply for the core vtt: termination power supply for pci express interface vddcaux: auxiliary power supply vddr: digital power supply for the i/o the typical power consumption of pi7c9x7958 is about 0.9 watt. 9.3. ac specifications table 9-3 transmitter characteristics symbol description min typical max. unit voltage parameters output voltage compliance @ typical swing v tx-diffp (peak-to-peak, single ended) 400 500 600 mv v tx-diff a v tx-diffpp (peak-to-peak, differential) 800 1000 1200 mv v sw supported tx output voltage range (pp, differential) 700 b 1400 c mv v ol low-level output voltage v tt - 1.5 *v tx-diffp v v oh high-level output voltage v tt - 0.5v tx-diffp v v tx-cm-ac transmit common-mode voltage in l0 0.50 v tt - v tx-diffp 1.45 v v tx-cm-hiz transmit common-mode voltage in l0s (tx) & l1 v tx-cm-ac v v tx-de-ratio de-emphasized differential output voltage 0 -7.96 db 11-0039
pi7c9x7958 pci express? octal uart datasheet page 67 of 71 march 2011 ? revision 1.4 pericom semiconductor symbol description min typical max. unit v tx-idle-diffp electric idle differentia l peak voltage 20 mv v tx-rcv-detect voltage change during receive detection v tx-diffp mv rl tx-diff transmitter differential return loss 10 db rl tx-cm transmitter common mode return loss 6 db z ose single-ended output impedance 40 50 60 ? z tx-diff-dc dc differential tx impedance 80 100 120 ? t tx-rise, ttx-fall rise / fall time of txp, txn outputs 80 110 d ps jitter parameters ui unit interval 399.88 400 400.12 ps t tx-max-jitter transmitter total jitter (peak-to-peak) 0.30 e ui t tx-eye minimum tx eye width (1 - t tx-max-jitter ) 0.70 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.15 ui timing parameters l tlat-10 transmitter data latency (for n=10) 9 11 ui l tlat-20 transmitter data latency (for n=20) 9 11 ui l tx-skew transmitter data skew between any 2 lanes 0 2 + 200ps ui t tx-idle-set-to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set 8 ns t eiexit time to exit electrical idle (l0s) state into l0 12 16 ns t bten time from asserting beacontxen to beacon being transmitted on the lane 30 80 ns a. measured with vtt = 1.2v, hi drv=?0?,lowdrv=?0? and dtx=?0000?. b. minimum swing assumes lodrv = 1, hidrv = 0 and dtx =1100 c. max swing assumes lodrv = 0, hidrv = 1, dtx = 0010, vtt = 1.8v d. as measured between 20% and 80% points. will depend on package characteristics. e. measured using pci express compliance pattern table 9-4 receiver characteristics symbol description min typical max. unit voltage parameters v rx-diffp-p differential input voltage (peak-to-peak) 170 1200 mv v rx-idle-det-diffp-p differential input threshold voltage (peak-to-peak) to assert txidledetect output 65 175 mv v rx-cm-ac receiver common-mode voltage for ac-coupling 0 150 mv t rx-rise, trx-fall rise time / fall time of rxp, rxn inputs 160 ps z rx-diff-dc differential input impedance (dc) 80 100 120 ? z rx-com-dc single-ended input impedance 40 50 60 ? z rx-com-initial-dc initial input common mode impedance (dc) 5 50 60 ? z rx-com-high-imp-dc powered down input common mode impedance (dc) 200k ? rl rx-diff receiver differential return loss a 10 db rl rx-cm receiver common mode return loss b 6 db jitter parameters t rx-max-jitter receiver total jitter tolerance 0.65 ui t rx-eye minimum receiver eye width 0.35 ui t rx-eye-median-to-max-jitter maximum time between jitter median and max deviation from median 0.325 ui timing parameters lrlat-10 receiver data latency for n=10 28 29 bits 11-0039
pi7c9x7958 pci express? octal uart datasheet page 68 of 71 march 2011 ? revision 1.4 pericom semiconductor symbol description min typical max. unit lrlat-20 receiver data latency for n=20 49 60 bits trx-skew receiver data skew between any 2 lanes 0 1 c bits tbddly beacon-activity on channel to detection of beacon d 200 us trx-idle_enter delay from detection of electrical idle condition on the channel to assertion of txidledetect output 10 20 ns trx-idle_exit delay from detection of l0s to l0 transition to deassertion of txidledetect output 5 10 ns a. over a frequency range of 50 mhz to 1.25 ghz. b. over a frequency range of 50 mhz to 1.25 ghz. c. assuming synchronized bit streams at the respective receiver inputs. d. this is a function of beacon frequency 11-0039
pi7c9x7958 pci express? octal uart datasheet page 69 of 71 march 2011 ? revision 1.4 pericom semiconductor 10. clock scheme the pi7c9x7958 requires 100mhz differential clock inputs through clkinp and clkinn pins as shown in the following table. table 10-1 input clock requirements symbol description min typical max. unit clkin freq reference input clock range - 100 - mhz clkin dc duty cycle of input clock 40 50 60 % t r , t f rise/fall time of input clock - - 0.2 rcui a v sw differential input voltage swing (zero-to-peak) 0.4 0.8 v a. rcui (reference clock unit interval) refers to the reference clock period 11-0039
pi7c9x7958 pci express? octal uart datasheet page 70 of 71 march 2011 ? revision 1.4 pericom semiconductor 11. package information the package of the pi7c9x7958 is a 160-pin lfbga. the ball pitch is 0.8mm and the ball size is 0.5mm. the following are the package information and mechanical dimensions. 1 : n o i t p i r c s e d : e d o c e g a k c a p 2031 - d p : # l o r t n o c t n e m u c o d d : n o i s i v e r 1 1 / 5 2 / 2 0 : e t a d nb160 160-ball low profile fine pitch ball grid array (lfbga) notes: 1) all dimensions are in millimeters 2) jedec# is mo-205f/ae figure 11-1 package outline drawing 11-0039
pi7c9x7958 pci express? octal uart datasheet page 71 of 71 march 2011 ? revision 1.4 pericom semiconductor 12. order information part number temperature range package pb-free & green pi7c9x7958 nbe -40 o to 85 o c (industrial temperature) 160-pin lfbga 12mm x 12mm ye s pi 7c 9x7958 nb e blank=standard e=pb-fr ee and gr een package code blank=standard =revision device type device number pi=per ic om family 11-0039

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